Notes to tables: (1) See the Operating Requ" />
參數(shù)資料
型號: EPF10K100EQI208-2
廠商: Altera
文件頁數(shù): 47/100頁
文件大?。?/td> 0K
描述: IC FLEX 10K FPGA 100K 208-PQFP
產(chǎn)品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 72
系列: FLEX-10KE®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計: 49152
輸入/輸出數(shù): 147
門數(shù): 257000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
50
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Notes to tables:
(1)
(2)
Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2.0 V for input currents
less than 100 mA and periods shorter than 20 ns.
(3)
Numbers in parentheses are for industrial-temperature-range devices.
(4)
Maximum VCC rise time is 100 ms, and VCC must rise monotonically.
(5)
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are
powered.
(6)
Typical values are for T A = 25° C, VCCINT = 2.5 V, and VCCIO = 2.5 V or 3.3 V.
(7)
These values are specified under the FLEX 10KE Recommended Operating Conditions shown in Tables 20 and 21.
(8)
The FLEX 10KE input buffers are compatible with 2.5-V, 3.3-V (LVTTL and LVCMOS), and 5.0-V TTL and CMOS
signals. Additionally, the input buffers are 3.3-V PCI compliant when VCCIO and VCCINT meet the relationship shown
(9)
The IOH parameter refers to high-level TTL, PCI, or CMOS output current.
(10) The IOL parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
as well as output pins.
(11) This value is specified for normal device operation. The value may vary during power-up.
(12) This parameter applies to -1 speed-grade commercial-temperature devices and -2 speed-grade-industrial
temperature devices.
(13) Pin pull-up resistance values will be lower if the pin is driven higher than VCCIO by an external source.
(14) Capacitance is sample-tested only.
Table 23. FLEX 10KE Device Capacitance
Symbol
Parameter
Conditions
Min
Max
Unit
CIN
Input capacitance
VIN = 0 V, f = 1.0 MHz
10
pF
CINCLK Input capacitance on
dedicated clock pin
VIN = 0 V, f = 1.0 MHz
12
pF
COUT
Output capacitance
VOUT = 0 V, f = 1.0 MHz
10
pF
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