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參數(shù)資料

型號(hào)：	EPF10K100EQI208-2
廠商：	Altera
文件頁(yè)數(shù)：	8/100頁(yè)
文件大?。?/td>	0K
描述：	IC FLEX 10K FPGA 100K 208-PQFP
產(chǎn)品培訓(xùn)模塊：	Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝：	72
系列：	FLEX-10KE®
LAB/CLB數(shù)：	624
邏輯元件/單元數(shù)：	4992
RAM 位總計(jì)：	49152
輸入/輸出數(shù)：	147
門數(shù)：	257000
電源電壓：	2.375 V ~ 2.625 V
安裝類型：	表面貼裝
工作溫度：	-40°C ~ 100°C
封裝/外殼：	208-BFQFP
供應(yīng)商設(shè)備封裝：	208-PQFP（28x28）

Altera Corporation

FLEX 10KE Embedded Programmable Logic Devices Data Sheet

EABs provide flexible options for driving and controlling clock signals.

Different clocks and clock enables can be used for reading and writing to

the EAB. Registers can be independently inserted on the data input, EAB

output, write address, write enable signals, read address, and read enable

signals. The global signals and the EAB local interconnect can drive write

enable, read enable, and clock enable signals. The global signals,

dedicated clock pins, and EAB local interconnect can drive the EAB clock

signals. Because the LEs drive the EAB local interconnect, the LEs can

control write enable, read enable, clear, clock, and clock enable signals.

An EAB is fed by a row interconnect and can drive out to row and column

interconnects. Each EAB output can drive up to two row channels and up

to two column channels; the unused row channel can be driven by other

LEs. This feature increases the routing resources available for EAB

outputs (see Figures 2 and 4). The column interconnect, which is adjacent

to the EAB, has twice as many channels as other columns in the device.

Logic Array Block

An LAB consists of eight LEs, their associated carry and cascade chains,

LAB control signals, and the LAB local interconnect. The LAB provides

the coarse-grained structure to the FLEX 10KE architecture, facilitating

efficient routing with optimum device utilization and high performance

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