參數(shù)資料
型號: EPF10K100EQI208-2
廠商: Altera
文件頁數(shù): 40/100頁
文件大?。?/td> 0K
描述: IC FLEX 10K FPGA 100K 208-PQFP
產(chǎn)品培訓(xùn)模塊: Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝: 72
系列: FLEX-10KE®
LAB/CLB數(shù): 624
邏輯元件/單元數(shù): 4992
RAM 位總計: 49152
輸入/輸出數(shù): 147
門數(shù): 257000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
44
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
All FLEX 10KE devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. FLEX 10KE devices can also be
configured using the JTAG pins through the BitBlaster or ByteBlasterMV
download cable, or via hardware that uses the JamTM STAPL
programming and test language. JTAG boundary-scan testing can be
performed before or after configuration, but not during configuration.
FLEX 10KE devices support the JTAG instructions shown in Table 15.
The instruction register length of FLEX 10KE devices is 10 bits. The
USERCODE register length in FLEX 10KE devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined. Tables 16 and 17
show the boundary-scan register length and device IDCODE information
for FLEX 10KE devices.
Table 15. FLEX 10KE JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device
pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through a selected device to adjacent devices during normal
device operation.
USERCODE
Selects the user electronic signature (USERCODE) register and places it between the
TDI
and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
IDCODE
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
ICR Instructions
These instructions are used when configuring a FLEX 10KE device via JTAG ports with
a BitBlaster or ByteBlasterMV download cable, or using a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
Table 16. FLEX 10KE Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EPF10K30E
690
EPF10K50E
EPF10K50S
798
EPF10K100E
1,050
EPF10K130E
1,308
EPF10K200E
EPF10K200S
1,446
相關(guān)PDF資料
PDF描述
EMC60DRYS CONN EDGECARD 120PS DIP .100 SLD
AMC26DRAN CONN EDGECARD 52POS .100 R/A DIP
AX1000-1FGG484I IC FPGA AXCELERATOR 1M 484-FBGA
AX1000-1FG484I IC FPGA AXCELERATOR 1M 484-FBGA
AMC26DRAH CONN EDGECARD 52POS .100 R/A DIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K100EQI208-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI208-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC