參數(shù)資料
型號(hào)： EPF10K100EQI208-2
廠商： Altera
文件頁(yè)數(shù)： 33/100頁(yè)
文件大小： 0K
描述： IC FLEX 10K FPGA 100K 208-PQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 72
系列： FLEX-10KE®
LAB/CLB數(shù)： 624
邏輯元件/單元數(shù)： 4992
RAM 位總計(jì)： 49152
輸入/輸出數(shù)： 147
門數(shù)： 257000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-PQFP（28x28）
38
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
ClockLock &
ClockBoost
Features
To support high-speed designs, FLEX 10KE devices offer optional
ClockLock and ClockBoost circuitry containing a phase-locked loop (PLL)
used to increase design speed and reduce resource usage. The ClockLock
circuitry uses a synchronizing PLL that reduces the clock delay and skew
within a device. This reduction minimizes clock-to-output and setup
times while maintaining zero hold times. The ClockBoost circuitry, which
provides a clock multiplier, allows the designer to enhance device area
efficiency by resource sharing within the device. The ClockBoost feature
allows the designer to distribute a low-speed clock and multiply that clock
on-device. Combined, the ClockLock and ClockBoost features provide
significant improvements in system performance and bandwidth.
All FLEX 10KE devices, except EPF10K50E and EPF10K200E devices,
support ClockLock and ClockBoost circuitry. EPF10K50S and
EPF10K200S devices support this circuitry. Devices that support Clock-
Lock and ClockBoost circuitry are distinguished with an “X” suffix in the
ordering code; for instance, the EPF10K200SFC672-1X device supports
this circuit.
The ClockLock and ClockBoost features in FLEX 10KE devices are
enabled through the Altera software. External devices are not required to
use these features. The output of the ClockLock and ClockBoost circuits is
not available at any of the device pins.
The ClockLock and ClockBoost circuitry locks onto the rising edge of the
incoming clock. The circuit output can drive the clock inputs of registers
only; the generated clock cannot be gated or inverted.
The dedicated clock pin (GCLK1) supplies the clock to the ClockLock and
ClockBoost circuitry. When the dedicated clock pin is driving the
ClockLock or ClockBoost circuitry, it cannot drive elsewhere in the device.
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to the GCLK1 pin. In the
Altera software, the GCLK1 pin can feed both the ClockLock and
ClockBoost circuitry in the FLEX 10KE device. However, when both
circuits are used, the other clock pin cannot be used.
相關(guān)PDF資料
PDF描述
EMC60DRYS CONN EDGECARD 120PS DIP .100 SLD
AMC26DRAN CONN EDGECARD 52POS .100 R/A DIP
AX1000-1FGG484I IC FPGA AXCELERATOR 1M 484-FBGA
AX1000-1FG484I IC FPGA AXCELERATOR 1M 484-FBGA
AMC26DRAH CONN EDGECARD 52POS .100 R/A DIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPF10K100EQI208-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI208-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-1DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-2DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPF10K100EQI240-3DX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*