參數資料
型號: EPF10K100EQI208-2
廠商: Altera
文件頁數: 53/100頁
文件大小: 0K
描述: IC FLEX 10K FPGA 100K 208-PQFP
產品培訓模塊: Three Reasons to Use FPGA's in Industrial Designs
標準包裝: 72
系列: FLEX-10KE®
LAB/CLB數: 624
邏輯元件/單元數: 4992
RAM 位總計: 49152
輸入/輸出數: 147
門數: 257000
電源電壓: 2.375 V ~ 2.625 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
56
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Figure 28. Synchronous Bidirectional Pin External Timing Model
Tables 24 through 28 describe the FLEX 10KE device internal timing
parameters. Tables 29 through 30 describe the FLEX 10KE external timing
parameters and their symbols.
PRN
CLRN
DQ
PRN
CLRN
DQ
PRN
CLRN
DQ
Dedicated
Clock
Bidirectional
Pin
Output Register
tINSUBIDIR
tOUTCOBIDIR
tXZBIDIR
tZXBIDIR
tINHBIDIR
OE Register
Input Register
Table 24. LE Timing Microparameters (Part 1 of 2)
Symbol
Parameter
Condition
tLUT
LUT delay for data-in
tCLUT
LUT delay for carry-in
tRLUT
LUT delay for LE register feedback
tPACKED
Data-in to packed register delay
tEN
LE register enable delay
tCICO
Carry-in to carry-out delay
tCGEN
Data-in to carry-out delay
tCGENR
LE register feedback to carry-out delay
tCASC
Cascade-in to cascade-out delay
tC
LE register control signal delay
tCO
LE register clock-to-output delay
tCOMB
Combinatorial delay
tSU
LE register setup time for data and enable signals before clock; LE register
recovery time after asynchronous clear, preset, or load
tH
LE register hold time for data and enable signals after clock
tPRE
LE register preset delay
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