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參數(shù)資料
型號(hào): EVAL-ADUC7036QSPZ
廠商: Analog Devices Inc
文件頁數(shù): 111/132頁
文件大小: 0K
描述: BOARD EVAL FOR ADUC7036
設(shè)計(jì)資源: EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝: 1
系列: QuickStart™ PLUS 套件
主要目的: 電源管理,電池監(jiān)控器
嵌入式: 是,MCU,16/32 位
已用 IC / 零件: ADuC7036
已供物品: 板,線纜,文檔,仿真器,電源,軟件
ADuC7036
Rev. C | Page 8 of 132
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RSLAVE
Slave termination resistance
20
30
47
VSERIAL DIODE28
Voltage drop at the serial diode, DSER_INT
0.4
0.7
1
V
Symmetry of Transmit Propagation
Delay1
VDD (min) = 7 V
2
+2
μs
Receive Propagation Delay1
VDD (min) = 7 V
6
μs
Symmetry of Receive Propagation
Delay1
VDD (min) = 7 V
2
+2
μs
LIN VERSION 1.3 SPECIFICATION
Bus load conditions (CBUS
||RBUS):1 nF||1 kΩ;
6.8 nF
||660 Ω; 10 nF||500 Ω
Slew rate
Dominant and recessive edges, VBAT = 18 V
1
2
3
V/μs
Slew rate
Dominant and recessive edges, VBAT = 7 V
0.5
3
V/μs
Symmetry of rising and falling edge, VBAT = 18 V
5
+5
μs
Symmetry of rising and falling edge, VBAT = 7 V
4
+4
μs
LIN VERSION 2.0 SPECIFICATION
Bus load conditions (CBUS||RBUS): 1 nF||1 kΩ;
6.8 nF||660 Ω; 10 nF||500 Ω
D1
Duty Cycle 1,
THREC (MAX) = 0.744 × VBAT,
THDOM (MAX) = 0.581 × VBAT,
VSUP = 7 V…18 V; tBIT = 50 μs,
D1 = tBUS_REC (MIN)/(2 × tBIT)
0.396
D2
Duty Cycle 2,
THREC (MIN) = 0.284 × VBAT,
THDOM (MIN) = 0.422 × VBAT,
VSUP = 7 V…18 V; tBIT = 50 μs,
D2 = tBUS_REC (MAX)/(2 × tBIT)
0.581
BSD INPUT/OUTPUT29
Baud Rate
1164
1200
1236
Bits/sec
Input leakage current
Input high = VDD, or input low = IO_VSS
50
+50
μA
VOL, Output Low Voltage
1.2
V
VOH, Output High Voltage
0.8 VDD
V
IO(SC) Short-Circuit Output Current
VBSD = VDD = 12 V
50
80
120
mA
VINL, Input Low Voltage
1.8
V
VINH, Input High Voltage
0.7 VDD
V
WAKE UP
RLOAD = 300 Ω, CBUS = 91 nF, RLIMIT = 39 Ω
Supply voltage range at which the WU pin is
functional
7
18
V
Input Leakage Current
Input high = VDD
0.4
2.1
mA
Input low = IO_VSS
50
+50
μA
VOH30
Output high level
5
V
VOL30
Output low level
2
V
VIH
Input high level
4.6
V
VIL
Input low level
1.2
V
Monoflop Timeout
Timeout period
0.6
1.3
2
sec
IO(SC) Short-Circuit Output Current
100
140
mA
SERIAL TEST INTERFACE
RLOAD = 500 Ω, CBUS = 2.4 nF, RLIMIT = 39 Ω
Baud Rate
40
kbps
Input Leakage Current
Input high = VDD or input low = IO_VSS
50
+70
μA
VDD
Supply voltage range for which STI is functional
7
18
V
VOH
Output high level
0.6 VDD
V
VOL
Output low level
0.4 VDD
V
VIH
Input high level
0.6 VDD
V
VIL
Input low level
0.4 VDD
V
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