參數(shù)資料
型號(hào)： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 120/132頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計(jì)資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 88 of 132
GPIO Port2 Control Register
Name: GP2CON
Address: 0xFFFF0D08
Default Value: 0x01000000
Access: Read/write
Function: This 32-bit MMR selects the pin function for each Port2 pin.
Table 61. GP2CON MMR Bit Designations
Bit
Description
31 to 25
Reserved. These bits are reserved and should be written as 0 by user code.
24
GPIO_13 function select bit.
Set to 1 by user code to route the STI data output to the STI pin.
If this bit is cleared to 0 by user code, then the STI data is not routed to the external STI pin even if the STI interface is enabled
correctly.
23 to 21
Reserved. These bits are reserved and should be written as 0 by user code.
20
GPIO_12 function select bit.
Set to 1 by user code to route the UART TxD (transmit data) to the LIN/BSD data pin. This configuration is used in LIN mode.
Cleared by user code to 0 to route the LIN/BSD transmit data to an internal general-purpose I/O (GPIO_12) pad, which can then
be written via the GP2DAT MMR. This configuration is used in BSD mode to allow user code to write output data to the BSD
interface, and it can also be used to support diagnostic write capability to the high voltage I/O pins (see HVCFG1[2:0] in Table 75).
19 to 17
Reserved. These bits are reserved and should be written as 0 by user code.
16
GPIO_11 function select bit.
Set to 1 by user code to route input data from the LIN/BSD interface to both the LIN/BSD hardware timing/synchronization logic
and to the UART RxD (receive data). This mode must be configured by user code when using LIN or BSD modes.
Cleared by user code to 0 to internally disable the LIN/BSD input data path. In this configuration GPIO_11 is used to support
diagnostic readback on all external high voltage I/O pins (see HVCFG1[2:0] in Table 75).
15 to 5
Reserved. These bits are reserved and should be written as 0 by user code.
4
GPIO_8 function select bit.
Set to 1 by user code to route the LIN/BSD input data to the GPIO_8 pin. This mode can be used to drive the LIN transceiver
interface as a standalone component without any interaction from MCU or UART.
Cleared by user code to 0 to configure the GPIO_8 pin as a general-purpose I/O (GPIO) pin.
3 to 1
Reserved. These bits are reserved and should be written as 0 by user code.
0
GPIO_7 function select bit.
Set by user code to 1 to route data driven into the GPIO_7 pin through the on-chip LIN transceiver to be output at the LIN/BSD
pin. This mode can be used to drive the LIN transceiver interface as a standalone component without any interaction from MCU
or UART.
Cleared by user code to 0 to configure the GPIO_7 pin as a general-purpose I/O (GPIO) pin.
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