參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 95/132頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 65 of 132
POWCON Register
Name: POWCON
Address: 0xFFFF0408
Default Value: 0x79
Access: Read/write
Function: This 8-bit register allows user code to dynamically enter various low power modes and modify the CD divider that controls the
speed of the ARM7TDMI core.
Table 46. POWCON MMR Bit Designations
Bit
Description
7
Precision 131 kHz input enable.
Set by the user to enable the precision 131 kHz input enable. The precision 131 kHz oscillator must also be enabled using HVCFG0[6].
Setting this bit increases current consumption by approximately 50 μA. It should be disabled when not in use.
Cleared by the user to power-down the precision 131 kHz input enable.
6
XTAL power-down.
Set by the user to enable the external crystal circuitry.
Cleared by the user to power down the external crystal circuitry.
5
PLL power-down. Timer peripherals power down if driven from the PLL output clock. Timers driven from an active clock source
remain in normal power mode.
Set by default and set by hardware on a wake-up event.
Cleared to 0 to power down the PLL. The PLL cannot be powered down if either the core or peripherals are enabled: Bit 3, Bit 4,
and Bit 5 must be cleared simultaneously.
4
Peripherals power-down. The peripherals that are powered down by this bit are as follows: SRAM, Flash/EE memory and GPIO
interfaces, and SPI and UART serial ports.
Set by default and/or by hardware on a wake-up event. The wake-up timer (Timer2) can still be active if driven from a low power
oscillator even if this bit is set.
Cleared to power down the peripherals. The peripherals cannot be powered down if the core is enabled: Bit 3 and Bit 4 must be
cleared simultaneously. LIN can still respond to wake-up events even if this bit is cleared.
3
Core power-down. If user code powers down the MCU, include a dummy MCU cycle after the power-down command is written to
POWCON.
Set by default, and set by hardware on a wake-up event.
Cleared to power down the ARM core.
CD core clock divider bits.
000 = 20.48 MHz, 48.83 ns.
001 = 10.24 MHz, 97.66 ns (this is default setting on power up).
010 = 5.12 MHz, 195.31 ns.
011 = 2.56 MHz, 390.63 ns.
100 = 1.28 MHz, 781.25 ns.
101 = 640 kHz, 1.56 μs.
110 = 320 kHz, 3.125 μs.
2 to 0
111 = 160 kHz, 6.25 μs.
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