參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 21/132頁
文件大小： 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 117 of 132
LIN Hardware Synchronization Status Register
Name: LHSSTA
Address: 0xFFFF0780
Default Value: 0x00000000
Access: Read only
Function: This LHS status register is a 32-bit register whose bits reflect the current operating status of the LIN interface.
Table 92. LHSSTA MMR Bit Designations
Bit
Description
31 to 7
Reserved. These read only bits are reserved for future use.
6
Rising edge detected (BSD mode only).
Set to 1 by hardware to indicate a rising edge has been detected on the BSD bus.
Cleared to 0 after user code reads the LHSSTA MMR.
5
LHS reset complete flag.
Set to 1 by hardware to indicate an LHS reset command has completed successfully.
Cleared to 0 after user code reads the LHSSTA MMR.
4
Break field error.
Set to 1 by hardware and generates an LHS interrupt (IRQEN[7]) when the 12-bit break timer (LHSVAL1) register
overflows to indicate the LIN bus has stayed low too long, thus indicating a possible LIN bus error.
Cleared to 0 after user code reads the LHSSTA MMR.
3
LHS compare interrupt.
Set to 1 by hardware when the value in LHSVAL0 (LIN synchronization bit timer) equals the value in the LHSCMP register.
Cleared to 0 after user code reads the LHSSTA MMR.
2
Stop condition interrupt.
Set to 1 by hardware when a stop condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
1
Start condition interrupt.
Set to 1 by hardware when a start condition is detected.
Cleared to 0 after user code reads LHSSTA MMR.
0
Break timer compare interrupt.
Set to 1 by hardware when a valid LIN break condition is detected. A LIN break condition is generated when the LIN
break timer value reaches the break timer compare value (see the LHSVAL1 in the LIN Hardware Synchronization Break
Timer1 Register section for more information).
Cleared to 0 after user code reads the LHSSTA MMR.
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