參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 112/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計(jì)資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 80 of 132
TIMER3—WATCHDOG TIMER
Timer3 has two modes of operation: normal mode and watch-
dog mode. The watchdog timer is used to recover from an
illegal software state. When enabled, Timer3 requires periodic
servicing to prevent it from forcing a reset of the processor.
Timer3 reloads the value from T3LD when Timer3 overflows.
Normal Mode
The Timer3 in normal mode is identical to Timer0 in 16-bit mode
of operation, except for the clock source. The clock source is the
low power 32.768 kHz oscillator, which is scalable by a factor of
1, 16, or 256.
Watchdog Mode
Watchdog mode is entered by setting T3CON[5]. Timer3
decrements from the timeout value present in the T3LD register
until 0 is reached. The maximum timeout is 512 seconds, using
a maximum prescaler/256 and full scale in T3LD.
User software should not configure a timeout period of less
than 30 ms to avoid any conflict with Flash/EE memory page
erase cycles that require 20 ms to complete a single page erase
cycle and kernel execution.
If T3VAL reaches 0, a reset or an interrupt occurs, depending
on T3CON[1]. To avoid a reset or an interrupt event, any value
must be written to T3CLRI before T3VAL reaches 0. This
reloads the counter with T3LD and begins a new timeout period.
When watchdog mode is entered, T3LD and T3CON are
write protected. These two registers cannot be modified until
a power-on reset event resets the watchdog timer. After any
other reset event, the watchdog timer continues to count. The
watchdog timer should be configured in the initial lines of user
code to avoid an infinite loop of watchdog resets. User software
should configure only a minimum timeout period of 30 ms.
Timer3 is automatically halted during JTAG debug access and
recommences counting only after JTAG has relinquished control
of the ARM7 core. By default, Timer3 continues to count during
power-down. This can be disabled by setting Bit 0 in T3CON.
It is recommended to use the default value; that is, the watchdog
timer continues to count during power-down.
Timer3 Interface
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CLRI, and T3CON. T3LD and T3VAL are 16-bit registers
(Bit 0 to Bit 15) and hold 16-bit unsigned integers. T3VAL is a
read only register. T3CLRI is an 8-bit register. Writing any value
to this register clears the Timer3 interrupt in normal mode or
resets a new timeout period in watchdog mode. T3CON is the
configuration MMR described in Table 56.
Timer3 Load Register
Name: T3LD
Address: 0xFFFF0360
Default Value: 0x0040
Access: Read/write
Function: This 16-bit MMR holds the Timer3 reload value.
Timer3 Clear Register
Name: T3CLRI
Address: 0xFFFF036C
Access: Write only
Function: This 8-bit, write only MMR is written (with
any value) by user code to refresh (reload) Timer3 in watchdog
mode to prevent a watchdog timer reset event.
Timer3 Value Register
Name: T3VAL
Address: 0xFFFF0364
Default Value: 0x0040
Access: Read only
Function: This 16-bit, read only MMR holds the current Timer3
count value.
PRESCALER
1, 16, 256
TIMER3 IRQ
WATCHDOG RESET
16-BIT
UP/DOWN COUNTER
LOW POWER
32.768kHz
16-BIT LOAD
TIMER3
VALUE
07474-
035
Figure 38. Timer3 Block Diagram
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