參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 131/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 98 of 132
High Voltage Configuration0 Register
Name: HVCFG0
Address: Indirectly addressed via the HVCON high voltage interface
Default Value: 0x00
Access: Read/write
Function: This 8-bit register controls the function of high voltage circuits on the ADuC7036. This register is not an MMR and does not
appear in the MMR memory map. It is accessed via the HVCON register interface. Data to be written to this register is loaded via the
HVDAT MMR, and data is read back from this register via the HVDAT MMR.
Table 74. HVCFG0 Bit Designations
Bit
Description
7
Wake-up/STI thermal shutdown disable.
Set to 1 to disable the automatic shutdown of the wake-up/STI driver when a thermal event occurs.
Cleared to 0 to enable the automatic shutdown of the wake-up/STI driver when a thermal event occurs.
6
Precision oscillator enable bit.
Set to 1 to enable the precision 131 kHz oscillator. The oscillator start-up time is typically 70 μs (including a high
voltage interface latency of 10 μs).
Cleared to 0 to power down the precision 131 kHz oscillator.
5
Bit serial device (BSD) mode enable bit.
Set to 1 to disable the internal (LIN) pull-up and configure the LIN/BSD pin for BSD operation.
Cleared to 0 to enable the internal (LIN) pull-up resistor on the LIN/BSD pin.
4
Wake-up (WU) assert bit.
Set to 1 to assert the external WU pin high.
Cleared to 0 to pull the external WU pin low via an internal 10 kΩ pull-down resistor.
3
Power supply monitor (PSM) enable bit.
Set to 1 to enable the power supply (voltage at the VDD pin) monitor. If IRQ3 (IRQEN[16]) is enabled, the PSM
generates an interrupt if the voltage at the VDD pin drops below 6 V.
Cleared to 0 to disable the power supply (voltage at the VDD pin) monitor.
2
Low voltage flag (LVF) enable bit.
Set to 1 to enable the LVF function. The low voltage flag can be interrogated via HVMON[3] after power-up to
determine if the REG_DVDD voltage previously dropped below 2.1 V.
Cleared to 0 to disable the LVF function.
1 to 0
LIN operating mode. These bits enable/disable the LIN driver.
00 = LIN disabled.
01 = reserved (not LIN V2.0 compliant).
10 = LIN enabled.
11 = reserved, not used.
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