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| 型號： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設(shè)計(jì)資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 119 of 132
Bit
Description
5
Enable compare interrupt bit.
Set to 1 by user code to generate an LHS interrupt (IRQEN[7]) when the value in LHSVAL0 (the LIN synchronization bit timer)
equals the value in the LHSCMP register. The LHS compare interrupt bit, LHSSTA[3], is set when this interrupt occurs. This
configuration is used in BSD write mode to allow user code to correctly time the output pulse widths of BSD bits to be transmitted.
Cleared to 0 by user code to disable compare interrupts.
4
Enable stop interrupt.
Set to 1 by user code to generate an interrupt when a stop condition occurs.
Cleared to 0 by user code to disable interrupts when a stop condition occurs.
3
Enable start interrupt.
Set to 1 by user code to generate an interrupt when a start condition occurs.
Cleared to 0 by user code to disable interrupts when a start condition occurs.
2
LIN sync enable bit.
Set to 1 by user code to enable LHS functionality.
Cleared to 0 by user code to disable LHS functionality.
1
Edge counter clear bit.
Set to 1 by user code to clear the internal edge counters in the LHS peripheral.
Cleared automatically to 0 after a 15 μs delay.
0
LHS reset bit.
Set to 1 by user code to reset all LHS logic to default conditions.
Cleared automatically to 0 after a 15 μs delay.
1 In BSD mode, LHSCON0[6] is set to 1. Because of the finite propagation delay in the BSD transmit (from the MCU to the external pin) and receive (from the external pin
to the MCU) paths, user code must not switch between BSD write and read modes until the MCU confirms that the external BSD pin is deasserted. Failure to adhere to
this recommendation may result in the generation of an inadvertent break condition interrupt after user code switches from BSD write mode to BSD read mode. A
stop condition interrupt can be used to ensure that this scenario is avoided.
LIN Hardware Synchronization Control Register 1
Name: LHSCON1
Address: 0xFFFF078C
Default Value: 0x00000032
Access: Read/write
Function: This 32-bit LHS control register, in conjunction with the LHSCON0 register, is used to configure the LIN mode of operation.
Table 94. LHSCON1 MMR Bit Designations
Bit
Description
31 to 8
Reserved. These bits are reserved for future use and should be written as 0 by user software.
7 to 4
LIN stop edge count. Set by user code to the number of falling or rising edges on which to stop the internal LIN
synchronization counter. The stop value of this counter can be read by user code using LHSVAL0. The type of edge, either
rising or falling, is configured by LHSCON0[7]. The default value of these bits is 0x3, which configures the hardware to
stop counting on the third falling edge. Note that the first falling edge is considered to be the falling edge at the start of
the LIN break pulse.
3 to 0
LIN start edge count. These four bits are set by user code to the number of falling edges that must occur before the
internal LIN synchronization timer starts counting. The stop value of this counter can be read by user code using
LHSVAL0. The default value of these bits is 0x2, which configures the hardware to start counting on the second falling
edge. Note that the first falling edge is considered to be the falling edge at the start of the LIN break pulse.
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