參數(shù)資料
型號(hào)： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 98/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計(jì)資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 68 of 132
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 16 interrupt sources on the ADuC7036 that are con-
trolled by the interrupt controller. Most interrupts are generated
from the on-chip peripherals, such as the ADC and UART. The
ARM7TDMI CPU core recognizes interrupts as one of only two
types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is managed
through nine interrupt-related registers, with four dedicated to
IRQ and four dedicated to FIQ. An additional MMR is used to
select the programmed interrupt source. The bits in each IRQ
and FIQ register represent the same interrupt source as described
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid interrupt
sources are serviced.
The interrupt generation route through the ARM7TDMI core is
shown in Figure 32.
Consider an example in which Timer0 is configured to generate
a timeout every 1 ms. After the first 1 ms timeout, FIQSIG[2] or
IRQSIG[2] is set and can be cleared only by writing to T0CLRI.
If Timer0 is not enabled in either IRQEN or FIQEN, then FIQSTA/
IRQSTA[2] is not set and an interrupt does not occur. However,
if Timer0 is enabled in either IRQEN or FIQEN, then either
FIQSTA[2] or IRQSTA[2] is set or an interrupt (FIQ or IRQ)
occurs.
Note that the IRQ and FIQ bit definitions in the CPSR control
interrupt recognition only by the ARM core and not by the peri-
pherals. For example, if Timer2 is configured to generate an
IRQ via IRQEN, the IRQ interrupt bit is set (disabled) in the
CPSR and the ADuC7036 is powered down. When an interrupt
occurs, the peripherals wake up, but the ARM core remains
powered down. This is equivalent to POWCON = 0x71. The
ARM core can then be powered up only by a reset event.
Table 50. IRQ/FIQ MMRs Bit Designations
Bit
Description
Comments
0
All interrupts OR’ed (FIQ only)
1
SWI: not used in IRQEN/IRQCLR and FIQEN/FIQCLR
2
Timer0
See the Timer0—Lifetime Timer section.
3
Timer1
See the Timer1 section.
4
Timer2 or wake-up timer
See the Timer2—Wake-Up Timer section.
5
Timer3 or watchdog timer
See the Timer3—Watchdog Timer section.
6
Timer4 or STI timer
See the Timer4—STI Timer section.
7
LIN hardware
8
Flash/EE interrupt
9
PLL lock
See the System Clocks section.
10
ADC
See the 16-Bit,
11
UART
See the UART Serial Interface section.
12
SPI master
13
XIRQ0 (GPIO IRQ0)
See the General-Purpose I/O section.
14
XIRQ1 (GPIO IRQ1)
See the General-Purpose I/O section.
15
Reserved
16
IRQ3 high voltage IRQ
High voltage interrupt; see the High Voltage Peripheral Control Interface
section.
17
SPI slave
18
XIRQ4 (GPIO IRQ4)
See the General-Purpose I/O section.
19
XIRQ5 (GPIO IRQ5)
See the General-Purpose I/O section.
20 to
32
Reserved
Reserved.
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