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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 30 of 92
EXPLANATION OF TYPICAL PERFORMANCE PLOTS
The plots presented in the Typical Performance Characteristics
section illustrate typical performance of the ADuC832 under
various operating conditions.
Figure 16 and Figure 17 show typical ADC integral nonlinearity
(INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz, and the
typically worst-case errors in both plots are slightly less than
0.3 LSBs.
Figure 18 and Figure 19 show the variation in worst-case
positive (WCP) INL and worst-case negative (WCN) INL vs.
external reference input voltage.
Figure 20 and Figure 21 show typical ADC differential nonlinear-
ity (DNL) errors from ADC Code 0 to Code 4095 at 5 V and
3 V supplies, respectively. The ADC is using its internal refer-
ence (2.5 V) and operating at a sampling rate of 152 kHz, and
the typically worst-case errors in both plots is slightly less than
0.2 LSBs.
Figure 22 and Figure 23 show the variation in worst-case
positive (WCP) DNL and worst-case negative (WCN) DNL
vs. external reference input voltage.
Figure 24 shows a histogram plot of 10,000 ADC conversion
results on a dc input with VDD = 5 V. The plot illustrates an
excellent code distribution pointing to the low noise
performance of the on-chip precision ADC.
Figure 25 shows a histogram plot of 10,000 ADC conversion
results on a dc input for VDD = 3 V. The plot again illustrates a
very tight code distribution of 1 LSB with the majority of codes
appearing in one output pin.
Figure 26 and Figure 27 show typical FFT plots for the ADuC832.
These plots were generated using an external clock input. The
ADC is using its internal reference (2.5 V) sampling a full-scale,
10 kHz sine wave test tone input at a sampling rate of 149.79 kHz.
The resultant FFTs shown at 5 V and 3 V supplies illustrate an
excellent 100 dB noise floor, 71 dB or greater signal-to-noise
ratio (SNR), and THD greater than 80 dB.
Figure 28 and Figure 29 show typical dynamic performance vs.
external reference voltages. Again, excellent ac performance can
be observed in both plots with some roll-off being observed as
VREF falls below 1 V.
Figure 30 shows typical dynamic performance vs. sampling
frequency. SNR levels of 71 dB are obtained across the sampling
range of the ADuC832.
Figure 31 shows the voltage output of the on-chip temperature
sensor vs. temperature. Although the initial voltage output at
25°C can vary from part to part, the resulting slope of 2 mV/°C is
constant across all parts.
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