參數(shù)資料
型號(hào)： EVAL-ADUC832QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 69/92頁(yè)
文件大?。?/td> 0K
描述： KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC832
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
其它名稱： EVAL-ADUC832QS
EVAL-ADUC832QS-ND
Data Sheet
ADuC832
Rev. B | Page 71 of 92
TCON (Timer/Counter 0 and Timer/Counter 1 Control
Register)
SFR Address:
88H
Power-On Default Value:
00H
Bit Addressable:
Yes
TIMER/COUNTER 0 AND TIMER/COUNTER 1 DATA
REGISTERS
Each timer consists of two 8-bit registers. These can be used as
independent registers or combined to be a single 16-bit register,
depending on the timer mode configuration.
TH0 and TL0
TH0 is the Timer 0 high byte and TL0 is the low byte. The SFR
addresses for TH0 and TL0 are 8CH and 8AH, respectively.
TH1 and TL1
TH1 is the Timer 1 high byte and TH0 is the low byte. The SFR
addresses for TH1 and TL1 are 8DH and 8BH, respectively.
Table 37. TCON SFR Bit Designations
Bit
Name
Description
[7]
TF1
Timer 1 overflow flag.
Set by hardware on a Timer/Counter 1 overflow.
Cleared by hardware when the program counter (PC) vectors to the interrupt service routine.
[6]
TR1
Timer 1 run control bit.
Set by the user to turn on Timer/Counter 1.
Cleared by the user to turn off Timer/Counter 1.
[5]
TF0
Timer 0 overflow flag.
Set by hardware on a Timer/Counter 0 overflow.
Cleared by hardware when the PC vectors to the interrupt service routine.
[4]
TR0
Timer 0 run control bit.
Set by the user to turn on Timer/Counter 0.
Cleared by the user to turn off Timer/Counter 0.
[3]
External Interrupt 1 (INT1) flag.
Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT1, depending on the state of Bit IT1.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If
level-activated, the external requesting source controls the request flag, rather than the on-chip hardware.
[2]
IT11
External Interrupt 1 (IE1) trigger type.
Set by software to specify edge-sensitive detection (that is, a 1-to-0 transition).
Cleared by software to specify level-sensitive detection (that is, zero level).
[1]
External Interrupt 0 (INT0) flag.
Set by hardware by a falling edge or zero level being applied to external interrupt Pin INT0, depending on the state of Bit IT0.
Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated.
If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware.
[0]
IT01
External Interrupt 0 (IE0) trigger type.
Set by software to specify edge-sensitive detection (that is, 1-to-0 transition).
Cleared by software to specify level-sensitive detection (that is, zero level).
1
These bits are not used in the control of Timer/Counter 0 and Timer/Counter 1, but are used instead in the control and monitoring of the external INT0 and INT1
interrupt pins.
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