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參數(shù)資料
| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 73/92頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關產品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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Data Sheet
ADuC832
Rev. B | Page 75 of 92
UART SERIAL INTERFACE
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered, meaning it
can commence reception of a second byte before a previously
received byte has been read from the receive register. However,
if the first byte still has not been read by the time reception of
the second byte is complete, the first byte is lost. The physical
interface to the serial data network is via the RXD and TXD
pins, and the SFR interface to the UART is comprised of SBUF
and SCON.
SBUF
The serial port receive and transmit registers are both accessed
through the SBUF SFR (SFR address = 99H). Writing to SBUF
loads the transmit register and reading SBUF accesses a
physically separate receive register.
SCON (UART SERIAL PORT CONTROL REGISTER)
SFR Address:
98H
Power-On Default Value:
00H
Bit Addressable:
Yes
Table 40. SCON SFR Bit Designations
Bit
Name
Description
[7:6]
SM[0:1]
UART serial mode select bits. These bits select the serial port operating mode as follows:
SM0
SM1
Selected Operating Mode
0
Mode 0: shift register, fixed baud rate (Core_CLK/2)
0
1
Mode 1: 8-bit UART, variable baud rate
1
0
Mode 2: 9-bit UART, fixed baud rate (Core_CLK/64) or (Core_CLK/32)
1
Mode 3: 9-bit UART, variable baud rate
[5]
SM2
Multiprocessor communication enable bit.
Enables multiprocessor communication in Mode 2 and Mode 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set,
RI is not activated if a valid stop bit was not received. If SM2 is cleared, RI is set as soon as the byte of data has been
received. In Mode 2 or Mode 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI
is set as soon as the byte of data has been received.
[4]
REN
Serial port receive enable bit.
Set by user software to enable serial port reception.
Cleared by user software to disable serial port reception.
[3]
TB8
Serial Port Transmit Bit 9.
The data loaded into TB8 is the ninth data bit that is transmitted in Mode 2 and Mode 3.
[2]
RB8
Serial Port Receiver Bit 9.
The ninth data bit received in Mode 2 and Mode 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8.
[1]
TI
Serial port transmit interrupt flag.
Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Mode 1, Mode 2, and Mode 3.
TI must be cleared by user software.
[0]
RI
Serial port receive interrupt flag.
Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Mode 1, Mode 2, and Mode 3.
RI must be cleared by software.
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