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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓模塊： | Process Control |
| 標準包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 56 of 92
PWM MODES OF OPERATION
MODE 0: PWM DISABLED
The PWM is disabled, allowing P2.6 and P2.7 to be used as normal.
MODE 1: SINGLE VARIABLE RESOLUTION PWM
In Mode 1, both the pulse length and the cycle time (period)
are programmable in user code, allowing the resolution of the
PWM to be variable.
PWM1H/PWM1L sets the period of the output waveform. Reduc-
ing PWM1H/PWM1L reduces the resolution of the PWM output
but increases the maximum output rate of the PWM. (for example,
setting PWM1H/PWM1L to 65,536 gives a 16-bit PWM with a
maximum output rate of 266 Hz (16.78 MHz/65,536). Setting
PWM1H/PWM1L to 4096 gives a 12-bit PWM with a maxi-
mum output rate of 4096 Hz (16.78 MHz/4096).
PWM0H/PWM0L sets the duty cycle of the PWM output
waveform, as shown in Figure 57.
P2.7
PWM COUNTER
PWM1H/L
0
PWM0H/L
02987-
046
Figure 57. PWM Mode 1
MODE 2: TWIN 8-BIT PWM
In Mode 2, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are both programmable. The maximum
resolution of the PWM output is eight bits.
PWM1L sets the period for both PWM outputs. Typically, this
is set to 255 (FFH) to give an 8-bit PWM although it is possible
to reduce this as necessary. A value of 100 can be loaded here to
give a percentage PWM (that is, the PWM is accurate to 1%).
The outputs of the PWM at P2.6 and P2.7 are shown in Figure 58.
As can be seen, the output of PWM0 (P2.6) goes low when the
PWM counter equals PWM0L. The output of PWM1 (P2.7)
goes high when the PWM counter equals PWM1H and goes
low again when the PWM counter equals PWM0H. Setting
PWM1H to 0 ensures that both PWM outputs start simulta-
neously.
P2.7
P2.6
PWM COUNTER
PWM1H
0
PWM1L
PWM0H
PWM0L
02987-
047
Figure 58. PWM Mode 2
MODE 3: TWIN 16-BIT PWM
In Mode 3, the PWM counter is fixed to count from 0 to 65,536,
giving a fixed 16-bit PWM. Operating from the 16.78 MHz core
clock results in a PWM output rate of 256 Hz. The duty cycle of the
PWM outputs at P2.6 and P2.7 is independently programmable.
As shown in Figure 59, while the PWM counter is less than
PWM0H/PWM0L, the output of PWM0 (P2.6) is high. Once
the PWM counter equals PWM0H/PWM0L, PWM0 (P2.6)
goes low and remains low until the PWM counter rolls over.
Similarly, while the PWM counter is less than PWM1H/
PWM1L, the output of PWM1 (P2.7) is high. Once the PWM
counter equals PWM1H/PWM1L, PWM1 (P2.7) goes low and
remains low until the PWM counter rolls over.
In this mode, both PWM outputs are synchronized, that is, once
the PWM counter rolls over to 0, both PWM0 (P2.6) and
PWM1 (P2.7) go high.
P2.7
P2.6
PWM COUNTER
PWM1H/L
0
65,536
PWM0H/L
02987-
048
Figure 59. PWM Mode 3
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