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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/92頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 42 of 92
When the DMA conversions are completed, the ADC interrupt
bit, ADCI, is set by hardware and the external SRAM contains
the new ADC conversion results as shown in Figure 45. Note
that no result is written to the last two memory locations.
When the DMA mode logic is active, it takes the responsibility
of storing the ADC results away from both the user and ADuC832
core logic. As it writes the results of the ADC conversions to
external memory, it takes over the external memory interface
from the core. Thus, any core instructions that access the external
memory while DMA mode is enabled do not gain access to it.
The core executes the instructions, which take the same time to
execute, but do not gain access to the external memory.
NO CONVERSION
RESULT WRITTEN HERE
CONVERSION RESULT
FOR ADC CH 3
CONVERSION RESULT
FOR TEMP SENSOR
CONVERSION RESULT
FOR ADC CH 5
CONVERSION RESULT
FOR ADC CH 2
00000AH
000000H
STOP COMMAND
1
0
1
0
1
0
1
0
1
02987-
034
Figure 45. Typical External Memory Configuration Post-ADC DMA Operation
The DMA logic operates from the ADC clock and uses pipelin-
ing to perform the ADC conversions and to access the external
memory at the same time. The time it takes to perform one
ADC conversion is called a DMA cycle. The actions performed
by the logic during a typical DMA cycle are shown in Figure 46.
WRITE ADC RESULT
CONVERTED DURING
PREVIOUS DMA CYCLE
READ CHANNEL ID
TO BE CONVERTED DURING
NEXT DMA CYCLE
CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE
DMA CYCLE
02987-
035
Figure 46. DMA Cycle
From Figure 46, it can be seen that during one DMA cycle, the
following actions are performed by the DMA logic:
An ADC conversion is performed on the channel whose
ID was read during the previous cycle.
The 12-bit result and the channel ID of the conversion
performed in the previous cycle is written to the external
memory.
The ID of the next channel to be converted is read from
external memory.
For the previous example, the complete flow of events is shown
in Figure 46. Because the DMA logic uses pipelining, it takes
three cycles before the first correct result is written out.
MICRO-OPERATION DURING ADC DMA MODE
During ADC DMA mode, the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, note that MCU core accesses to
Port 0 and Port 2 (which are being used by the DMA controller)
are gated off during ADC DMA mode of operation. This means
that even though the instruction that accesses the external Port 0 or
Port 2 appears to execute, no data is seen at these external ports
as a result. Note that during DMA to the internally contained
XRAM, Port 0 and Port 2 are available for use.
The only case in which the MCU is able to access XRAM during
DMA is when the internal XRAM is enabled and the section of
RAM to which the DMA ADC results are being written to lies
in an external XRAM. Then the MCU is able to access only the
internal XRAM. This is also the case for use of the extended
stack pointer.
The MicroConverter core can be configured with an interrupt
to be triggered by the DMA controller when it has finished
filling the requested block of RAM with ADC results, allowing
the service routine for this interrupt to postprocess data without
any real-time timing constraints.
ADC OFFSET AND GAIN CALIBRATION
COEFFICIENTS
The ADuC832 has two ADC calibration coefficients, one for
offset calibration and one for gain calibration. Both the offset
and gain calibration coefficients are 14-bit words, and are each
stored in two registers located in the special function register
(SFR) area. The offset calibration coefficient is divided into
ADCOFSH (six bits) and ADCOFSL (eight bits) and the gain
calibration coefficient is divided into ADCGAINH (six bits)
and ADCGAINL (eight bits).
The offset calibration coefficient compensates for dc offset
errors in both the ADC and the input signal. Increasing the
offset coefficient compensates for positive offset, and effectively
pushes the ADC transfer function down. Decreasing the offset
coefficient compensates for negative offset, and effectively
pushes the ADC transfer function up. The maximum offset that
can be compensated is typically ±5% of VREF, which equates to
typically ±125 mV with a 2.5 V reference.
Similarly, the gain calibration coefficient compensates for dc
gain errors in both the ADC and the input signal. Increasing the
gain coefficient compensates for a smaller analog input signal
range and scales the ADC transfer function up, effectively
increasing the slope of the transfer function. Decreasing the
gain coefficient compensates for a larger analog input signal
range and scales the ADC transfer function down, effectively
decreasing the slope of the transfer function. The maximum
analog input signal range for which the gain coefficient can
compensate is 1.025 × VREF and the minimum input range is
0.975 × VREF, which equates to typically ±2.5% of the reference
voltage.
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