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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 68/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 70 of 92
TIMERS/COUNTERS
The ADuC832 has three 16-bit timer/counters: Timer 0, Timer 1,
and Timer 2. The timer/counter hardware has been included on
chip to relieve the processor core of the overhead inherent in
implementing timer/counter functionality in software. Each
timer/counter consists of two 8-bit registers THx and TLx (x =
0, 1, and 2). All three can be configured to operate either as
timers or event counters.
In the timer function, the TLx register is incremented every
machine cycle. Thus, it can be thought of as counting machine
cycles. Because a machine cycle consists of 12 core clock
periods, the maximum count rate is 1/12 the core clock
frequency.
In a counter function, the TLx register is incremented by a 1-to-
0 transition at its corresponding external input pin, T0, T1, or
T2. In this function, the external input is sampled during S5P2
of every machine cycle. When the samples show a high in one
cycle and a low in the next cycle, the count is incremented. The
new count value appears in the register during S3P1 of the cycle
following the one in which the transition was detected. Because
two machine cycles (24 core clock periods) are needed to
recognize a 1-to-0 transition, the maximum count rate is 1/24
the core clock frequency. There are no restrictions on the duty
cycle of the external input signal, but to ensure that a given level
is sampled at least once before it changes, it must be held for a
minimum of one full machine cycle.
User configuration and control of all timer operating modes is
achieved via three SFRs: TMOD and TCON, which control and
configure Timer 0 and Timer 1, and T2CON, which controls and
configures Timer 2.
TMOD (Timer/Counter 0 and Timer/Counter 1 Mode
Register)
SFR Address:
89H
Power-On Default Value:
00H
Bit Addressable:
No
Table 36. TMOD SFR Bit Designations
Bit
Name
Description
[7]
Gate
Timer 1 gating control. Set by software to enable Timer/Counter 1 only while INT1 pin is high and TR1 control bit is set.
Cleared by software to enable Timer 1 whenever TR1 control bit is set.
[6]
C/T
Timer 1 timer or counter select bit. Set by software to select counter operation (input from T1 pin). Cleared by software to
select timer operation (input from internal system clock).
[5:4
M[1:0]
Timer 1 Mode Select Bit 1 and Bit 0.
M1
M0
Description
0
TH1 operates as an 8-bit timer/counter. TL1 serves as a 5-bit prescaler.
0
1
16-bit timer/counter. TH1 and TL1 are cascaded; there is no prescaler.
1
0
8-bit autoreload timer/counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows.
1
Timer/Counter 1 stopped.
[3]
Gate
Timer 0 gating control. Set by software to enable Timer/Counter 0 only while INT0 pin is high and TR0 control bit is set.
Cleared by software to enable Timer 0 whenever TR0 control bit is set.
[2]
C/T
Timer 0 timer or counter select bit. Set by software to select counter operation (input from T0 pin). Cleared by software to
select timer operation (input from internal system clock).
[1:0]
M[1:0]
Timer 0 Mode Select Bit 1 and Bit 0.
M1
M0
Description
0
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
0
1
16-bit timer/counter. TH0 and TL0 are cascaded; there is no prescaler.
1
0
8-Bit autoreload timer/counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows.
1
TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
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