參數(shù)資料
型號: EVAL-ADUC832QSZ
廠商: Analog Devices Inc
文件頁數(shù): 38/92頁
文件大小: 0K
描述: KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓(xùn)模塊: Process Control
標準包裝: 1
系列: QuickStart™ 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC832
所含物品: 評估板,線纜,電源,軟件和文檔
其它名稱: EVAL-ADUC832QS
EVAL-ADUC832QS-ND
Data Sheet
ADuC832
Rev. B | Page 43 of 92
CALIBRATING THE ADC
There are two hardware calibration modes provided that can be
easily initiated by user software. The ADCCON3 SFR is used to
calibrate the ADC. The typical bit (ADCCON3[1]) and the CS3
to CS0 bits (ADCCON2[3:0]) set up the calibration modes.
Device calibration can be initiated to compensate for significant
changes in operating conditions frequency, analog input range,
reference voltage, and supply voltages. In this calibration mode,
offset calibration uses the internal AGND selected via ADCCON2
register bits CS[3:0] = 1011, and gain calibration uses the internal
VREF selected by CS[3:0] = 1100. Offset calibration should be
executed first, followed by gain calibration.
System calibration can be initiated to compensate for both internal
and external system errors. To perform system calibration using
an external reference, tie system ground and reference to any
two of the six selectable inputs. Enable external reference mode
(ADCCON1[6]). Select the channel connected to AGND via
CS[3:0] and perform system offset calibration. Select the channel
connected to VREF via CS[3:0] and perform system gain calibration.
The ADC should be configured to use settings for an ADCCLK
of divide-by-16 and divide-by-4 acquisition clocks.
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