參數(shù)資料
型號(hào): EVAL-ADV7393EBZ
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 4/108頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADV7393 ENCODER
標(biāo)準(zhǔn)包裝: 1
系列: Advantiv®
主要目的: 視頻,視頻編碼器
已用 IC / 零件: ADV7393
已供物品:
相關(guān)產(chǎn)品: ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 101 of 108
Table 113. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 114. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
HIGH DEFINITION
Table 115. HD Configuration Scripts
Input Format
Input Data Width
Synchronization Format
Input Color Space
Output Color Space
Table Number
720p
8-bit DDR
EAV/SAV
YCrCb
YPrPb
720p
8-bit DDR
EAV/SAV
YCrCb
RGB
720p
10-bit DDR
EAV/SAV
YCrCb
YPrPb
720p
10-bit DDR
EAV/SAV
YCrCb
RGB
720p
16-bit SDR
EAV/SAV
YCrCb
YPrPb
720p
16-bit SDR
HSYNC/VSYNC
YCrCb
YPrPb
720p
16-bit SDR
EAV/SAV
YCrCb
RGB
720p
16-bit SDR
HSYNC/VSYNC
YCrCb
RGB
1080i
8-bit DDR
EAV/SAV
YCrCb
YPrPb
1080i
8-bit DDR
EAV/SAV
YCrCb
RGB
1080i
10-bit DDR
EAV/SAV
YCrCb
YPrPb
1080i
10-bit DDR
EAV/SAV
YCrCb
RGB
1080i
16-bit SDR
EAV/SAV
YCrCb
YPrPb
1080i
16-bit SDR
HSYNC/VSYNC
YCrCb
YPrPb
1080i
16-bit SDR
EAV/SAV
YCrCb
RGB
1080i
16-bit SDR
HSYNC/VSYNC
YCrCb
RGB
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