- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16570 > EVAL-ADV7393EBZ (Analog Devices Inc)BOARD EVAL FOR ADV7393 ENCODER PDF資料下載
參數(shù)資料
| 型號： | EVAL-ADV7393EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7393 ENCODER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當(dāng)前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 48 of 108
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 on either the rising or falling
edge of CLKIN. Pin P8/P6 is the LSB.
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
on the opposite edge of CLKIN. P8/P6 is the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57
Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 59. ED/HD-SDR Example Application
Figure 60. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with Pin P8/P6 being the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)
Figure 62 ED (at 54 MHz) Example Application
3FF
00
X
Y
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
P[15:8]/
P]15:6]
Cb0
06234-
055
3FF
00
XY
Cb0
Cr0
Y1
CLKIN
P[15:8]/
P[15:P6]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
06234-
056
MPEG2
DECODER
CLKIN
P[7:0]
P[15:8]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8
CrCb
8
Y
2
06234-
057
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8/10
2
YCrCb
06234-
058
3FF
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
P[15:8]/P[15:6]
NOTES
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
06234-
059
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
54MHz
ADV7392/
ADV7393
VSYNC,
HSYNC
YCrCb
8/10
YCrCb
INTERLACED TO
PROGRESSIVE
06234-
060
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK672M/2-3-R | CABLE MINI USB 5PIN 3M 2.0 VERS |
| AK669-18-BLACK-R | CABLE USB 1.1 A-A M-F BLACK 1.8M |
| H3AKH-1436G | IDC CABLE - HSC14H/AE14G/HPK14H |
| EET-UQ2C152DA | CAP ALUM 1500UF 160V 20% SNAP |
| ADP195-EVALZ | BOARD EVALUATION FOR ADP195 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADV739XFEZ | 功能描述:BOARD EVAL FOR ADV739XFEZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADV7400AEBM | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| EVAL-ADV7400EBM | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-ADV7400EBM-U2 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-ADV7401EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。