參數(shù)資料
型號(hào)： EVAL-ADV7393EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 72/108頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADV7393 ENCODER
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻編碼器
已用 IC / 零件： ADV7393
已供物品： 板
相關(guān)產(chǎn)品： ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP
ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 66 of 108
ED/HD Input
Sync Format
(Subaddress
0x30, Bit 2)
ED/HD VSYNC
Control
(Subaddress
0x34, Bit 2)
ED/HD Sync
Output Enable
(Subaddress
0x02, Bit 7)
SD Sync
Output Enable
(Subaddress
0x02, Bit 6)
Video Standard
Signal on VSYNC Pin
Duration
X
1
X
All ED/HD standards
except 525p
Pipelined ED/HD VSYNC
based on the vertical
counter
Aligned with
serration lines.
X
1
X
525p
Pipelined ED/HD VSYNC
based on the vertical
counter
Vertical blanking
interval.
1
In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.
2
X = don’t care.
LOW POWER MODE
Subaddress 0x0D, Bits[2:0]
For power-sensitive applications, the ADV739x supports an
Analog Devices, Inc., proprietary low power mode of operation.
To use this low power mode, the DACs must be operating in
full-drive mode (RSET = 510 , RL = 37.5 ). Low power mode is
not available in low-drive mode (RSET = 4.12 k, RL = 300 ).
Low power mode can be independently enabled or disabled on
each DAC using Subaddress 0x0D, Bits[2:0]. Low power mode
is disabled by default on all DACs.
In low-power mode, DAC current consumption is content
dependent and, on a typical video stream, it can be reduced by
as much as 40%. For applications requiring the highest possible
video performance, low power mode should be disabled.
CABLE DETECTION
Subaddress 0x10, Bits[1:0]
The ADV739x includes an Analog Devices proprietary cable
detection feature. The cable detection feature is available on
DAC 1 and DAC 2 when operating in full-drive mode (RSET =
510 , RL = 37.5 , assuming a connected cable). The feature is
not available in low-drive mode (RSET = 4.12 k, RL = 300 ).
For a DAC to be monitored, the DAC must be powered up in
Subaddress 0x00.
The cable detection feature can be used with all SD, ED, and
HD video standards. It is available for all output configurations,
that is, CVBS, Y-C, YPrPb, and RGB output configurations.
For CVBS/Y-C output configurations, both DAC 1 and DAC 2
are monitored; that is, the CVBS and Y-C luma outputs are
monitored. For YPrPb and RGB output configurations, only
DAC 1 is monitored; that is, the luma or green output is
monitored.
Once per frame, the ADV739x monitors DAC 1 and/or DAC 2,
updating Subaddress 0x10, Bit 0 and/or Bit 1, respectively. If a
cable is detected on one of the DACs, the relevant bit is set to 0.
If not, the bit is set to 1.
DAC AUTOPOWER-DOWN
Subaddress 0x10, Bit 4
For power-sensitive applications, a DAC autopower-down
feature can be enabled using Subaddress 0x10, Bit 4. This
feature is available only when the cable detection feature is
enabled.
With this feature enabled, the cable detection circuitry monitors
DAC 1 and/or DAC 2 once per frame and, if they are
unconnected, automatically powers down some or all of the
DACs. Which DAC or DACs are powered down depends on the
selected output configuration. For CVBS/Y-C output configur-
ations, if DAC 1 is unconnected, only DAC 1 powers down. If
DAC 2 is unconnected, DAC 2 and DAC 3 power down.
For YPrPb and RGB output configurations, if DAC 1 is uncon-
nected, all three DACs are powered down. DAC 2 is not monitored
for YPrPb and RGB output configurations.
Once per frame, DAC 1 and/or DAC 2 is monitored. If a cable is
detected, the appropriate DAC or DACs remain powered up for
the duration of the frame. If no cable is detected, the appropriate
DAC or DACs power down until the next frame, when the
process is repeated.
SLEEP MODE
Subaddress 0x00, Bit 0
In sleep mode, most of the digital I/O pins of the ADV739x are
disabled. For inputs, this means that the external data is
ignored, and internally the logic normally driven by a given
input is just tied low or high. This includes CLKIN.
For digital output pins, this means that the pin goes into tristate
(high impedance) mode.
There are some exceptions to allow the user to continue to
communicate with the part via I2C: the RESET, ALSB, SDA and
SCL pins are kept alive.
Most of the analogue circuitry is powered down when in sleep
mode. In addition, the cable detect feature no longer works as
the DACs are powered down.
Sleep mode is enabled using Subaddress 0x00, Bit 0.
相關(guān)PDF資料
PDF描述
AK672M/2-3-R CABLE MINI USB 5PIN 3M 2.0 VERS
AK669-18-BLACK-R CABLE USB 1.1 A-A M-F BLACK 1.8M
H3AKH-1436G IDC CABLE - HSC14H/AE14G/HPK14H
EET-UQ2C152DA CAP ALUM 1500UF 160V 20% SNAP
ADP195-EVALZ BOARD EVALUATION FOR ADP195
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-ADV739XFEZ 功能描述:BOARD EVAL FOR ADV739XFEZ RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
EVAL-ADV7400AEBM 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer
EVAL-ADV7400EBM 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-ADV7400EBM-U2 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-ADV7401EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*