- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄16570 > EVAL-ADV7393EBZ (Analog Devices Inc)BOARD EVAL FOR ADV7393 ENCODER PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADV7393EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 55/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7393 ENCODER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 50 of 108
DESIGN FEATURES
OUTPUT OVERSAMPLING
The ADV739x includes an on-chip phase-locked loop (PLL)
that allows for oversampling of SD, ED, and HD video data. By
default, the PLL is disabled. The PLL can be enabled using
Subaddress 0x00, Bit 1 = 0.
Table 40 shows the various oversampling rates supported in the
ADV739x.
External Sync Polarity
For SD and ED/HD modes, the ADV739x parts typically expect
HS and VS to be low during their respective blanking periods.
However, when the CEA861 compliance bit is enabled (0x39,
Bit 5 for ED/HD modes and 0x86, Bit 3 for SD modes), the part
expects the HS or VS to be active low or high depending on the
input format selected (0x30, Bits[7:3]).
If a different polarity other than the default is required for
ED/HD modes, 0x3A, Bits[2:0] can be used to invert PHSYNCB,
PVSYNCB or PBLANKB individually regardless of whether
CEA-861-B mode is enabled. It is not possible to invert
S_HSYNC or S_VSYNC.
Table 40. Output Oversampling Modes and Rates
Input Mode
(0x01, Bits[6:4])
PLL and Oversampling
Control (0x00, Bit 1)
SD/ED Oversample Rate
Select (0x0D, Bit 3)1
HD Oversample Rate
Select (0x31, Bit 1)1
Oversampling Mode
and Rate
000
SD
1
X
SD (2×)
000
SD
0
1
X
SD (8×)
000
SD
0
X
SD (16×)
001/010
ED
1
X
ED (1×)
001/010
ED
0
1
X
ED (4×)
001/010
ED
0
X
ED (8×)
001/010
HD
1
X
HD (1×)
001/010
HD
0
X
1
HD (2×)
001/010
HD
0
X
0
HD (4×)
111
ED (at 54 MHz)
1
X
ED (at 54 MHz) (1×)
111
ED (at 54 MHz)
0
1
X
ED (at 54 MHz) (4×)
111
ED (at 54 MHz)
0
X
ED (at 54 MHz) (8×)
1
X = don’t care
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK672M/2-3-R | CABLE MINI USB 5PIN 3M 2.0 VERS |
| AK669-18-BLACK-R | CABLE USB 1.1 A-A M-F BLACK 1.8M |
| H3AKH-1436G | IDC CABLE - HSC14H/AE14G/HPK14H |
| EET-UQ2C152DA | CAP ALUM 1500UF 160V 20% SNAP |
| ADP195-EVALZ | BOARD EVALUATION FOR ADP195 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADV739XFEZ | 功能描述:BOARD EVAL FOR ADV739XFEZ RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADV7400AEBM | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| EVAL-ADV7400EBM | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-ADV7400EBM-U2 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-ADV7401EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。