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| 型號(hào)： | EVAL-ADV7393EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 85/108頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV7393 ENCODER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
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ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 78 of 108
SD CLOSED CAPTIONING
Subaddress 0x91 to Subaddress 0x94
The ADV739x supports closed captioning conforming to the
standard television synchronizing waveform for color trans-
mission. When enabled, closed captioning is transmitted during
the blanked active line time of Line 21 of the odd fields and
Line 284 of the even fields. Closed captioning can be enabled
using Subaddress 0x83, Bits[6:5].
Closed captioning consists of a seven-cycle sinusoidal burst that
is frequency- and phase-locked to the caption data. After the
clock run-in signal, the blanking level is held for two data bits
and is followed by a Logic 1 start bit. Sixteen bits of data follow
the start bit. The data consists of two 8-bit bytes (seven data bits
and one odd parity bit per byte). The data for these bytes is
stored in SD closed captioning registers (Subaddress 0x93 to
Subaddress 0x94).
The ADV739x also supports the extended closed captioning
operation, which is active during even fields and encoded on
Line 284. The data for this operation is stored in SD closed
captioning registers (Subaddress 0x91 to Subaddress 0x92).
The ADV739x automatically generates all clock run-in signals
and timing that support closed captioning on Line 21 and Line 284.
All pixels inputs are ignored on Line 21 and Line 284 if closed
captioning is enabled.
The FCC Code of Federal Regulations (CFR) Title 47 Section
15.119 and EIA-608 describe the closed captioning information
for Line 21 and Line 284.
The ADV739x uses a single buffering method. This means that
the closed captioning buffer is only 1-byte deep. Therefore,
there is no frame delay in outputting the closed captioning data,
unlike other 2-byte deep buffering systems. The data must be
loaded one line before it is output on Line 21 and Line 284. A
typical implementation of this method is to use VSYNC to
interrupt a microprocessor, which in turn loads the new data
(two bytes) in every field. If no new data is required for
transmission, 0s must be inserted in both data registers; this is
called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21. Otherwise, a TV does not
recognize them. If there is a message such as “Hello World” that
has an odd number of characters, it is important to add a blank
character at the end to make sure that the end-of-caption,
2-byte control code lands in the same field.
Figure 103. SD Closed Captioning Waveform, NTSC
D0 TO D6
10.5 ± 0.25s
12.91s
7 CYCLES OF
0.5035MHz
CLOCK RUN-IN
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = FSC = 3.579545MHz
AMPLITUDE = 40 IRE
50 IRE
40 IRE
10.003s
27.382s
33.764s
BYTE 1
BYTE 0
TWO 7-BIT + PARITY
ASCII CHARACTERS
(DATA)
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
06234-
101
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| EVAL-ADV739XFEZ | 功能描述:BOARD EVAL FOR ADV739XFEZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADV7400AEBM | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit Intergrated Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
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| EVAL-ADV7400EBM-U2 | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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