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參數資料
| 型號： | EVAL-ADV7393EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 50/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7393 ENCODER |
| 標準包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關產品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
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ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 46 of 108
ADV7390/ADV7391 INPUT CONFIGURATION
The ADV7390/ADV7391 support a number of different input
modes. The desired input mode is selected using Subaddress 0x01,
Bits[6:4]. The ADV7390/ADV7391 default to standard definition
(SD) mode on power-up. Table 35 provides an overview of all
possible input configurations. Each input mode is described in
detail in this section. Note that the WLCSP option is only
configured to support SD as shown in Figure 51.
Table 35. ADV7390/ADV7391 Input Configuration
Input Mode
P7
P6
P5
P4
P3
P2
P1
P0
000
SD
YCrCb
010
ED/HD-DDR
YCrCb
111
ED (at 54 MHz)
YCrCb
STANDARD DEFINITION
Subaddress 0x01, Bits[6:4] = 000
SD YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 27 MHz. A 27 MHz clock signal must be
provided on the CLKIN pin. If required, external synchroni-
zation signals can be provided on the HSYNC and VSYNC pins.
Embedded EAV/SAV timing codes are also supported. The
ITU-R BT.601/656 input standard is supported. The interleaved
pixel data is input on Pin P7 to Pin P0, with Pin P0 being the LSB.
Figure 51. SD Example Application
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 010
Enhanced definition (ED) or high definition (HD) YCrCb data
can be input in an interleaved 4:2:2 format over an 8-bit DDR
bus. The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)
In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input
on Pin P7 to Pin P0 on either the rising or falling edge of CLKIN.
Pin P0 is the LSB.
The CrCb pixel data is also input on Pin P7 to Pin P0 on the
opposite edge of CLKIN. Pin P0 is the LSB.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 52
and Figure 53).
Figure 52. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 53. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 54. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format over
an 8-bit bus rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
Figure 55. ED (at 54 MHz) Input Sequence (EAV/SAV)
MPEG2
DECODER
CLKIN
P[7:0]
27MHz
YCrCb
ADV7390/
ADV7391
VSYNC,
HSYNC
2
8
06234-
049
3FF
00
XY
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
P[7:0]
Cb0
06234-
050
3FF
00
XY
Cb0
Cr0
Y1
CLKIN
P[7:0]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
06234-
051
MPEG2
DECODER
CLKIN
P[7:0]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7390/
ADV7391
VSYNC,
HSYNC
8
2
YCrCb
06234-
052
3FF
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
P[7:0]
06234-
053
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