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| 型號： | EVAL-ADV7393EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 56/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV7393 ENCODER |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻編碼器 |
| 已用 IC / 零件： | ADV7393 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | ADV7393BCPZ-ND - IC DAC VIDEO HDTV 10BIT 40LFCSP ADV7393BCPZ-REEL-ND - IC DAC ENCODER VID HDTV 40-LFCSP |
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Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 51 of 108
HD INTERLACE EXTERNAL HSYNC AND VSYNC
CONSIDERATIONS
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01
or higher, the user should set Subaddress 0x02, Bit 1 to high.
To ensure exactly correct timing in HD interlace modes when
using HSYNC and VSYNC synchronization signals. If this bit is
set to low, the first active pixel on each line is masked in HD
interlace modes and the Pr and Pb outputs are swapped when
using the YCrCb 4:2:2 input format. Setting Subaddress 0x02,
Bit 1 to low causes the encoder to behave in the same way as the
first version of silicon (that is, this setting is backward
compatible).
If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,
the setting of Subaddress 0x02, Bit 1 has no effect. In this
version of the encoder, the first active pixel is masked and the
Pr and Pb outputs are swapped when using YCrCb 4:2:2 input
format. To avoid these limitations, use the newer revision of
silicon or use a different type of synchronization.
These considerations apply only to the HD interlace modes
with external HSYNC and VSYNC synchronization (EAV/SAV
mode is not affected and always has exactly correct timing).
There is no negative effect in setting Subaddress 0x02, Bit 0 to
high, and this bit can remain high for all the other video
standards.
ED/HD TIMING RESET
Subaddress 0x34, Bit 0
An ED/HD timing reset is achieved by setting the ED/HD
timing reset control bit (Subaddress 0x34, Bit 0) to 1. In this
state, the horizontal and vertical counters remain reset. When
this bit is set back to 0, the internal counters resume counting.
This timing reset applies to the ED/HD timing counters only.
SD SUBCARRIER FREQUENCY LOCK
Subcarrier Frequency Lock (SFL) Mode
In subcarrier frequency lock (SFL) mode (Subaddress 0x84,
Bits[2:1] = 11), the ADV739x can be used to lock to an external
video source. The SFL mode allows the ADV739x to automatically
alter the subcarrier frequency to compensate for line length
variations. When the part is connected to a device such as an
ADV7403 video decoder that outputs a digital data stream in the
SFL format, the part automatically changes to the compensated
subcarrier frequency on a line-by-line basis (see Figure 63). This
digital data stream is 67 bits wide, and the subcarrier is contained
in Bit 0 to Bit 21. Each bit is two clock cycles long.
Figure 63. SD Subcarrier Frequency Lock Timing and Connections Diagram (Subaddress 0x84, Bits [2:1] = 11)
LLC1
SFL
P19 TO
P10
ADV7403
VIDEO
DECODER
CLKIN
SFL
PIXEL PORT5
RTC
LOW
128
TIME SLOT 01
13
0
14
21
19
FSC PLL INCREMENT2
VALID
SAMPLE
INVALID
SAMPLE
6768
0
RESET BIT4
RESERVED
ADV739x
8/LINE
LOCKED
CLOCK
5 BITS
RESERVED
1FOR EXAMPLE, VCR OR CABLE.
2FSC PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV73xx FSC DDS REGISTER IS
FSC PLL INCREMENTS BITS[21:0] PLUS BITS[0:9] OF SUBCARRIER FREQUENCY REGISTERS.
3SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE
4RESET ADV739x DDS.
5REFER TO THE ADV7390/ADV7391 AND ADV7392/ADV7393 INPUT CONFIGURATION TABLES FOR PIXEL DATA PIN ASSIGNMENTS.
COMPOSITE
VIDEO1
H/L TRANSITION
COUNT START
14 BITS
SUBCARRIER
PHASE
SEQUENCE
BIT3
DAC 1
DAC 2
DAC 3
4 BITS
RESERVED
06234-
064
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| EVAL-ADV739XFEZ | 功能描述:BOARD EVAL FOR ADV739XFEZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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