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| 型號(hào)： | GT-48208 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器) |
| 中文描述： | 先進(jìn)的交換式以太網(wǎng)控制器的10 10/100 BaseX（高級(jí)交換式10 10/100 BaseX以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 42/135頁(yè) |
| 文件大?。?/td> | 1619K |
| 代理商： | GT-48208 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
LEO
TECHNOLOGY
CONFI
D
ENTI
AL
--
DO
NOT
REPRODUCE
14
Revision 1.2
2.1
Pin Functions and Assignment
Table 2:
Pin Functions
Sy mbol
Ty pe
D e scr ipt io n
CPU Interface
Rst*
I
RESET: Active Low. Resets the GT-482xx to its initial state. This signal must
be asserted for at least 10 MII clock cycles. Upon reset deassertion, the GT-
482xx clears the internal empty list and the Address Table.
AClk
I
Internal Clock: This clock provides the timing for the GT-482xx internal
units. All units, except for the Serial interface and the CPU interface, use this
clock. This clock can vary between CClk and 66Mhz. AClk is also used to
clock the synchronous DRAM. AClk frequency must be no higher than 4x
CClk frequency.
CClk
I
CPU Clock: This clock provides the timing for the GT-482xx CPU interface.
The clock can vary between 16Mhz to 50Mhz. In unmanaged switch opera-
tion, CClk should be tied to the 25MHz 100Mbit PHY clock. CClk frequency
must not be lower than 25% of AClk frequency, and not higher than total
AClk frequency.
AD[31:0]
I/O
Address Data: 32-bit multiplexed CPU address and data lines. During the
first clock of the transaction, AD<31:2> contains a physical word address (30
bits). During subsequent clock cycles, AD<31:0> contains data.
Blast*
I
LAST in Burst: Indicates the last word in the burst. The maximum burst size
is 8 words. Blast* has alternate meanings depending on CPU mode.
Ready*
O
READY: Indicates that AD[31:0] lines contain valid data. Ready* has alter-
nate meanings depending on CPU mode. This output pin features an open-
collector driver and should be tied as “wired-OR” in multiple GT-482xx
designs.
Ads*
I
Address Strobe: Indicates that AD[31:0] holds addresses (when deas-
serted it holds data). Ads* has alternate meanings depending on CPU mode.
W/R*
I
Write Read: Indicates Write/Read transaction. The polarity of this pin is pro-
grammable depending on CPU mode.
Int*
O
Interrupt: Interrupt request line. Int* is asserted by the GT-482xx when one
(or more) of the unmasked bits in the Interrupt Cause registers are set.
BurstAddr[2:1]
I
BurstAddr: In 3041 mode, contains bits [3:2] of the physical-byte address.
In 64010/11 mode, contains bits [2:1] of the address. (See Table 16, “RESET
RdCen*/BurstAddr[0]
I/O
RdCen*/BurstAddr: Read Buffer Clock Enable / Burst Address - In 3041
mode, this output pin indicates to the 3041 that the GT-482xx placed valid
data on the AD bus. In 64010/11 mode, contains bit [0] of the address. When
programmed to be an output, this pin features an open-collector driver and
should be tied as “wired-OR” in multiple GT-482xx designs.
DRAM Interface
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