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| 型號： | GT-48208 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級交換式 10+10/100 BaseX以太網(wǎng)控制器) |
| 中文描述： | 先進(jìn)的交換式以太網(wǎng)控制器的10 10/100 BaseX（高級交換式10 10/100 BaseX以太網(wǎng)控制器） |
| 文件頁數(shù)： | 63/135頁 |
| 文件大?。?/td> | 1619K |
| 代理商： | GT-48208 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
GALI
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TECHNOLOGY
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Revision 1.2
33
7.
PACKET FORWARDING
This section details the procedures used to forward packets with the following conditions:
Unicast packet to a local port
Multicast packet to local ports and the CPU
Packet destined for the CPU (Multicast, or Unicast packet from the GT-482xx to the CPU)
Unicast/Multicast packet from the CPU to the GT-482xx
7.1
Forwarding a Unicast Packet to a Local Port
The sequence for forwarding a Unicast packet to a local port is as follows:
1.
The incoming packet is fed to the Rx FIFO (there is a 64x32-bit Rx FIFO for the 10M ports and 128x32-
bit Rx FIFO for the 100M ports) and is transferred to an empty block in the Receive Buffer area of DRAM.
2.
In parallel, an address recognition cycle is performed for both the DA and the SA. The GT-482xx uses
the DA’s corresponding Port Number to queue the packet to the appropriate local port.
3.
At the end of an error-free packet transfer, packet information is written to the appropriate port’s transmit
descriptor. This information includes the Byte Count and the Receive Buffer Block Address which is
pointed to by the Write Pointer.
4.
The Write Pointer of the outgoing port’s transmit descriptor is incremented. The GT-482xx transmits
whenever the Write Pointer is not equal to the Read Pointer.
5.
At the end of the packet transmit process, the GT-482xx increments the Read Pointer and clears the
appropriate bit in the Empty List.
7.2
Forwarding a Multicast Packet
The GT-482xx forwards Multicast packets to all local ports and the CPU using the same mechanism as described
for Unicast packets. The GT-482xx has the ability to forward Multicast packets to a management CPU for inter-
vention routing, if desired.
7.3
Forwarding a Packet to the CPU
Systems that utilize a CPU (CpuEn of the Global Control register) can receive packets from the GT-482xx using a
simple slave interface. This includes the following packet types:
Unicast packets destined for the CPU (port number in the Address Table equal to 14d)
Multicast packets
Unknown packets (if set by ForwUnk bit in the Global Control Register)
IGMP packets
BPDU messages
Sniffer packets when the CPU is the target sniffer
EASE packets
The CPU transmit descriptor queues are used to store the outgoing packets from the GT-482xx ports to the CPU,
and to pass New_Address messages to the CPU. The GT-482xx does not DMA packets to the CPU. The CPU
reads the descriptors and then accesses the buffer contents directly from the GT-482xx’s SDRAM. The GT-482xx
provides the CPU with one descriptor at a time (in a dedicated, single register). The CPU can then access the
packet in the SDRAM (read/write) and provide an End_Of_Packet message to the GT-482xx, in a dedicated regis-
ter so that the GT-482xx will free the buffer in DRAM.
There are two packet queues (high and low priority). Each queue has the following data structure components:
CPU_Tx_Hi/Low_Desc register. These two registers (one for high priority and one for the low-priority
queue) are loaded with the next descriptor. Each 64-bit register holds the next descriptor, a
New_Address message or an Errored Source address to the CPU. When the GT-482xx has a new CPU
descriptor, it attempts to write it into one of the CPU_Tx_Hi/Low_Desc registers (depending on priority).
The new descriptor is written to the register provided that bit 31 of the second word is cleared. Bit 31 of
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