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| 型號(hào)： | GT-48208 |
| 廠商： | Galileo Technology Services, LLC |
| 英文描述： | Advanced Switched Ethernet Controllers for 10+10/100 BaseX(高級(jí)交換式 10+10/100 BaseX以太網(wǎng)控制器) |
| 中文描述： | 先進(jìn)的交換式以太網(wǎng)控制器的10 10/100 BaseX（高級(jí)交換式10 10/100 BaseX以太網(wǎng)控制器） |
| 文件頁(yè)數(shù)： | 65/135頁(yè) |
| 文件大小： | 1619K |
| 代理商： | GT-48208 |
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GT-482xx Switched Ethernet Controllers for 10+10/100 BaseX
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mat that the Descriptor_Control block is expecting). The register holds the information needed to
enqueue the packet (as the CPU has already wrote the buffer contents) and a busy-bit in the second
word (bit 31). The busy-bit is set by the GT-482xx whenever the CPU writes to the register and reset by
the GT-482xx when it is ready to receive a new enqueue request.
The CPU is allowed to send a packet to a disabled port. The Tx watchdog timer will eventually remove the packet
from the Tx queue and release its buffer.
The recommended structure of an interrupt service routine that handles packets that are forwarded to the CPU is
as follows:
1.
Mask the interrupt for new packets by writing to the Interrupt Mask register the appropriate value.
2.
Clear the interrupt cause bit.
3.
Read CPU_Tx_Desc1
4.
Read CPU_Tx_Desc2
5.
Read the interrupt_cause register, and see if there is a new packet. If yes then repeat steps (1)-(4), oth-
erwise enable interrupt receiving by clearing the mask register and exit the ISR.
7.5
Intervention Mode
Intervention Mode permits software or hardware intervention in the packet routing decision mechanisms. A packet
that is determined to require “intervention” will be enqueued only to the CPU (overriding the DA port#, forw<14:0>
fields and VL decisions). This is supported for Multicast and for Unicast packets and is performed when the CPU
has set the SA <Is> or the DA <Id> intervention fields in the Address Table.
7.6
IGMP Packet Support
When Global_Control[IGMP_En]=1, the GT-482xx traps IGMP packets that are received on any of its ports using
IPv4 and partial IPv6 over Ethernet V2 or 802.3 SNAP encoded (LLC is AA-AA-03-00-00-00) and passes them to
the CPU. See Appendix A on page135 for an illustration of the Ethernet packet formats. The CPU can then pro-
gram the GT-482xx to efficiently switch/filter IP Multicast traffic. The CPU can send the GT-482xx a New_Address
message containing a Multicast-MAC entry that will include the correct forwarding mask for this Multicast address.
The GT-482xx performs the following algorithm on each of its 14 ports when forwarding IGMP packets:
If ((Global_control<Igmp_en>==1) AND (DA is Multicast or Broadcast) AND (Source is NOT CPU) AND
(Packet is IGMP)
THEN forward packet ONLY TO CPU, on high priority queue.
Packet can be identified as IGMP by the following algorithm:
(Format is Ethernet or SNAP) AND
(Ethertype is IP (0x0800)) AND (
(IP version == 4 AND Protocol ==IGMP (0x02)) OR
(IP version == 6 AND Payload type == IGMP (0x02)
)
7.7
CRC Generation
The GT-482xx includes a CRC generator for packets transmitted by the CPU. The CRC generator enhances sys-
tem performance by implementing the CPU intensive packet FCS calculation in hardware. The CRC generation is
not required for packets transferred between ports or devices, since the CRC is already appended to these pack-
ets.
CRC generation for CPU generated packets is enabled through the EnCRC bit in the Global Control register. In
addition, the CPU must set the GenCRC bit in the EnQueue1 register.
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