參數(shù)資料
型號(hào): HY5R256HC
英文描述: -|2.5V|8K|40|Direct RDRAM - 256M
中文描述: - |為2.5V | 8K的| 40 |直接RDRAM的- 256M
文件頁(yè)數(shù): 26/64頁(yè)
文件大?。?/td> 4542K
代理商: HY5R256HC
26
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Control Register Transactions
The RDRAM has two CMOS input pins SCK and CMD and
two CMOS input/output pins SIO0 and SIO1. These provide
serial access to a set of control registers in the RDRAM.
These control registers provide configuration information to
the controller during the initialization process. They also
allow an application to select the appropriate operating mode
of the RDRAM.
SCK (serial clock) and CMD (command) are driven by the
controller to all RDRAMs in parallel. SIO0 and SIO1 are
connected (in a daisy chain fashion) from one RDRAM to
the next. In normal operation, the data on SIO0 is repeated
on SIO1, which connects to SIO0 of the next RDRAM (the
data is repeated from SIO1 to SIO0 for a read data packet).
The controller connects to SIO0 of the first RDRAM.
Write and read transactions are each composed of four
packets, as shown in Figure 23: and Figure 24:. Each packet
consists of 16 bits, as summarized in Table 13 and Table 14.
The packet bits are sampled on the falling edge of SCK. A
transaction begins with a SRQ (Serial Request) packet. This
packet is framed with a 11110000 pattern on the CMD input
(note that the CMD bits are sampled on both the falling edge
and the rising edge of SCK). The SRQ packet contains the
SOP3..SOP0 (Serial Opcode) field, which selects the trans-
action type. The SDEV4..SDEV0 (Serial Device address)
selects one of the 32 RDRAMs. If SBC (Serial Broadcast) is
set, then all RDRAMs are selected. The SA (Serial Address)
packet contains a 12 bit address for selecting a control
register.
A write transaction has a SD (Serial Data) packet next. This
contains 16 bits of data that is written into the selected
control register. A SINT (Serial Interval) packet is last,
providing some delay for any side-effects to take place. A
read transaction has a SINT packet, then a SD packet. This
provides delay for the selected RDRAM to access the
control register. The SD read data packet travels in the oppo-
site direction (towards the controller) from the other packet
types. Because the RDRAM drivers data on the falling SCK
edge,the read data transmit windows is offset tSCYCLE/2
relative to the other packet types.The SCK cycle time will
accomodate the total delay.
Figure 23: Serial Write (SWR) Transaction to Control Register
SRQ - SWR command
1111
00000000...00000000
SRQ - SWR command
0000
SA
SA
SD
SD
SINT
SINT
00000000...00000000
00000000...00000000
00000000...00000000
SCK
CMD
SIO0
SIO1
T
4
T
36
T
20
T
52
T
68
Each packet is repeated
from SIO0 to SIO1
1
1
1
1
0
0
0
0
1111
next transaction
Figure 24: Serial Read (SRD) Transaction Control Register
SRQ - SRD command
1111
00000000...00000000
SRQ - SRD command
0000
SA
SA
SINT
SINT
SD
SD
00000000...00000000
00000000...00000000
00000000...00000000
SCK
CMD
SIO0
SIO1
T
4
T
36
T
20
T
52
T
68
First 3 packets are repeated
from SIO0 to SIO1
non-addressed RDRAMs pass
0/SD15..SD0/0 from SIO1 to SIO0
1
1
1
1
0
0
0
0
1111
next transaction
0
0
controller drives
SINT15..SINT0 / 17*Z/0 on SIO0
0
0
addressed RDRAM drives
0/SD15..SD0/0 on SIO0
相關(guān)PDF資料
PDF描述
HY5R288HC -|2.5V|8K|40|Direct RDRAM - 288M
HY5V16CF 1Mx16|3.3V|4K|H|SDR SDRAM - 16M
HY5V16CF-H x16 SDRAM
HY5V16CF-S x16 SDRAM
HY6116-10 x8 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5S2B6DLF-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLF-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S5B2BLF-6E 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM