參數(shù)資料
型號: HY5R256HC
英文描述: -|2.5V|8K|40|Direct RDRAM - 256M
中文描述: - |為2.5V | 8K的| 40 |直接RDRAM的- 256M
文件頁數(shù): 39/64頁
文件大?。?/td> 4542K
代理商: HY5R256HC
Rev.0.9 / Dec.2000
39
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
state with a RLX command. A RLX command may be given
in an ROWR, COLC , or COLX packet (see the left side of
Figure 46:). It is usually given after all banks of the RDRAM
have been precharged; if other banks are still activated, then
the RLX command would probably not be given.
If a broadcast ROWA packet or ROWR packet (with the
ATTN command) is received, the RDRAM’s power state
doesn’t change. If a broadcast ROWR packet with RLXR
command is received, the RDRAM goes to STBY.
Figure 47: shows the NAP entry sequence (left). NAP state
is entered by sending a NAPR command in a ROW packet.
A time t
ASN
is required to enter NAP state (this specification
is provided for power calculation purposes). The clock on
CTM/CFM must remain stable for a time t
CD
after the
NAPR command.
The RDRAM may be in ATTN or STBY state when the
NAPR command is issued. When NAP state is exited, the
RDRAM will return to the original starting state (ATTN or
STBY). If it is in ATTN state and a RLXR command is
specified with NAPR, then the RDRAM will return to STBY
state when NAP is exited.
Figure 47: also shows the PDN entry sequence (right). PDN
state is entered by sending a PDNR command in a ROW
packet. A time t
ASP
is required to enter PDN state (this spec-
ification is provided for power calculation purposes). The
clock on CTM/CFM must remain stable for a time t
CD
after
the PDNR command.
The RDRAM may be in ATTN or STBY state when the
PDNR command is issued. When PDN state is exited, the
RDRAM will return to STBY. After a PDN exit, the
RDRAM maybe consume power as if it is in ATTN state
until a RLX command is received.Also the curent and slew-
rate-control levels must be re-established.
The RDRAM’s write buffer must be retired with the appro-
priate COP command before NAP or PDN are entered. Also,
all the RDRAM’s banks must be precharged before NAP or
PDN are entered. The exception to this is if NAP is entered
with the NSR bit of the INIT register cleared (disabling self-
refresh in NAP). The commands for relaxing, retiring, and
precharging may be given to the RDRAM as late as the
ROPa0, COPa0, and XOPa0 packets in Figure 47:. No
broadcast packets nor packets directed to the RDRAM
entering Nap or PDN may overlay the quiet window. This
window extends for a time t
NPQ
after the packet with the
NAPR or PDNR command.
Figure 48: shows the NAP and PDN exit sequences. These
sequences are virtually identical; the minor differences will
be highlighted in the following description.
Before NAP or PDN exit, the CTM/CFM clock must be
stable for a time t
CE
. Then, on a falling and rising edge of
SCK, if there is a “ 01 ” on the CMD input, NAP or PDN
state will be exited. Also, on the falling SCK edge the SIO0
input must be at a 0 for NAP exit and 1 for PDN exit.
If the PSX bit of the INIT register is 0, then a device
PDEV5..0 is specified for NAP or PDN exit on the DQA5..0
pins. This value is driven on the rising SCK edge 0.5 or 1.5
SCK cycles after the original falling edge, depending upon
the value of the DQS bit of the NAPX register. If the PSX bit
of the INIT register is 1, then the RDRAM ignores the
PDEV5..0 address packet and exits NAP or PDN when the
wake-up sequence is presented on the CMD wire. The ROW
and COL pins must be quiet at a time t
S4
/t
H4
around the indi-
cated falling SCK edge (timed with the PDNX or NAPX
register fields). After that, ROW and COL packets may be
directed to the RDRAM which is now in ATTN or STBY
state.
Figure 45: Power State Transition Diagram
automatic
automatic
a
a
a
a
ATTNR
ATTNW
ATTN
STBY
SETR/CLRR
NAPR
Notation:
SETR/CLRR - SETR/CLRR Reset sequence in SRQ packets
PDNR - PDNR command in ROWR packet
NAPR - NAPR command in ROWR packet
RLXR - RLX command in ROWR packet
RLX - RLX command in ROWR,COLC,COLX packets
SIO0 - SIO0 input value
PDEV.CMD - (PDEV=DEVID)(CMD=01)
ATTN - ROWA packet (non-broadcast) or ROWR packet
(non-broadcast) with ATTN command
t
NLIMIT
NAP
NAPR RLXR
PDEV.CMDSIO0
PDNR
PDN
PDNR
PDEV.CMDSIO0
N
P
A
R
相關(guān)PDF資料
PDF描述
HY5R288HC -|2.5V|8K|40|Direct RDRAM - 288M
HY5V16CF 1Mx16|3.3V|4K|H|SDR SDRAM - 16M
HY5V16CF-H x16 SDRAM
HY5V16CF-S x16 SDRAM
HY6116-10 x8 SRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HY5S2B6DLF-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-BE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLFP-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S2B6DLF-SE 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM
HY5S5B2BLF-6E 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:256M (8Mx32bit) Mobile SDRAM