參數資料
型號： HY5R256HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 256M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 256M
文件頁數： 29/64頁
文件大?。?/td> 4542K
代理商： HY5R256HC
Rev.0.9 / Dec.2000
29
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
o 3.13 Write CCA and CCB Register
- These registers are
written with a value halfway between their minimum and
maximum values. This shortens the time needed for the
RDRAMs to reach their steady-state current control values in
stage 5.0.
o 3.14 Powerdown Exit
- The RDRAMs are in the PDN power
state at this point . Abroadcast PDNExit command is performed
by the SIO block to place the RDRAMs in the RLX(relax)
power state in which they are ready to receive ROW packets.
o 3.15 SETF
- Each RDRAM is given a SETF command
through teh SIO block. One of the operations performed by this
step is to generate a value SKIP register and fix the RDRAM to
particular read domain.
4.0 Controller Configuration
- This stage initializes the controller
block. Each step of this stae will set a field of the Confi-
gRMC[63:0] bus to the appropriate value. Other controller imple-
mentations will have similar initialization requirements and this
stage may be used as a guide.
o 4..1 Initial Read Data Offsets
- The configRMC bus is
written with a OL packet with a memory read command and
the Qpacket with the read data on the Channel. The value
written sets RMC.d1 to the minimum value permitted for the
system. The will be adjusted later in stage 6.0.
o 4.2 Configure Row/Column Timing
- This step determines
the values of the tRAS,MIN, tRP,MIN, tRC,MIN, tRCD,MIN,
tRR,MIN and tPP,MIN RDRAM timing parameters that are
present in the system. The ConfigRMC bus is written with
values that will be compatible with all RDRAM devices that
are present.
o 4.3 Set Refresh INterval
- This step determines the values of
the tREF, MAX RDRAM timing parameter that are present in
the system. The ConfigRMC bus is written with a value that
will be compatible with all RDRAM devices that are present.
o 4.4 Set Current Control Interval
- This step determines the
values of the tCCTRL,MAX RDRAM timing parameter that
are present in the system. The ConfigRMC bus is written with
value that will be compatible with all RDRAM devices that are
presnet.
o 4.5 Set Slew Rate Control Interval
- This step determines
the values of the tTEMP,MAX RDRAM timing parameter that
are present ing the system. The ConfigRMC bus is written with
a value that will be compatible with all RDRAM devices that
are present.
o 4.6Set bank/RCol AddressBits
- This step deterimines the
number of RDRAM bank, row and column address bits that are
present in the system.
It also determines the RDRAM core types (independent,
doubled or split) that are present. The ConfigRMC bus is
written with a value that will be compatiblel with all RDRAM
devices that are present.
5.0 RDRAM Current Control
- This step causes the INIT block to
generate a sequence of pulses which performs RDRAM mainte-
nance operations.
6.0 RDRAM Core, Read Domain Initialization
- This stage
completes the RDRAM initialization.
o 6.1 RDRAM Core Initialization
- A sequence of
192memory refresh transctions is performed in order to place
the cores of all RDRAMs into the proper operating state.
o 6.2 RDRAM Read Domain Initialization
- A memory write
and memory read transaction is performed to each RDRAM to
determine which read domain each RDRAM occupies. The
programmed delay of each RDRAM is then adjusted do the
total RDRAM read delay (propagation delay plus programmed
delayP is constant. The TPARM and TCDLYI registers of each
RDRAM are rewritten with the appropriate read delay values.
The ConfigRMC bus is also rewritten with an updated value.
7.0 Other RDRAM Register Fields
- This stage rewrites the INIT
register with the final values of the LSR, NSR and PSR fields.
In essence, the conroller must read all the read-only configuration
registers of all RDRAMs (or it must read the SPD device present on
each RIMM), it must process this information and then it must
write all the read-write registers to place the RDRAMs into the
proper operating mode.
Initialization Note [1]
: During the initialization process, it is
necessary for the controller to preform 128 current control opera-
tions (3xCAL, 1xCAL/SAM) and one temperature calibrate opera-
tion (TCEN/TCAL) after reset or after power down (PDN) exit.
Initialization Note [2]
: There are two classes of 64/72Mbit
RDRAM. They are distinguished by the “S28IECO” bit in the SPD.
The behavior of the RDRAM at initialization is slightly different
for the two types:
S28IECO=0: Upon powerup the device enters ATTN state. The
serial operDEVID match of the SBC bit (broadcast) to be set.
S28IECO=1: Upon powerup the device enters PDN state. The
serial operations SETR, CLRR and SETF require a SDEVID
match.
See the document detailing the reference initialization procedure
for more information on how to handle this in a system.
Initialization Note [3]
: After the step of equalizing the total read
delay of eac RDRAM has been completed (i.e. after the TCDLY0
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