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參數(shù)資料
| 型號(hào)： | HY5R256HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 256M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 256M |
| 文件頁(yè)數(shù)： | 62/64頁(yè) |
| 文件大?。?/td> | 4542K |
| 代理商： | HY5R256HC |
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62
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Glossary of Terms
ACT
Activate command from AV field.
activate
To access a row and place in sense amp.
adjacent
Two RDRAM banks which share sense
amps (also called doubled banks).
ASYM
CCA register field for RSL V
OL
/V
OH
.
Power state - ready for ROW/COL
packets.
ATTN
ATTNR
Power state - transmitting Q packets.
ATTNW
Power state - receiving D packets.
AV
Opcode field in ROW packets.
A block of 2
RBIT
2
CBIT
storage cells in the
core of the RDRAM.
bank
BC
Bank address field in COLC packet.
BBIT
CNFGA register field - # bank address
bits.
broadcast
An operation executed by all RDRAMs.
BR
Bank address field in ROW packets.
bubble
Idle cycle(s) on RDRAM pins needed
because of a resource constraint.
BYT
CNFGB register field - 8/9 bits per byte.
BX
Bank address field in COLX packet.
C
Column address field in COLC packet.
CAL
Calibrate (I
OL
) command in XOP field.
CNFGB register field - # column address
bits.
CBIT
CCA
Control register - current control A.
CCB
Control register - current control B.
CFM,CFMN
Clock pins for receiving packets.
Channel
ROW/COL/DQ pins and external wires.
CLRR
Clear reset command from SOP field.
CMD
CMOS pin for initialization/power control.
CNFGA
Control register with configuration fields.
CNFGB
Control register with configuration fields.
COL
Pins for column-access control.
COL
COLC,COLM,COLX packet on COL pins.
COLC
Column operation packet on COL pins.
COLM
Write mask packet on COL pins.
column
Rows in a bank or activated row in sense
amps have 2
CBIT
dualocts column storage.
command
A decoded bit-combination from a field.
COLX
Extended operation packet on COL pins.
controller
A logic-device which drives the
ROW/COL /DQ wires for a Channel of
RDRAMs.
COP
Column opcode field in COLC packet.
core
The banks and sense amps of an RDRAM.
CTM,CTMN
Clock pins for transmitting packets.
current control
Periodic operations to update the proper
I
OL
value of RSL output drivers.
D
Write data packet on DQ pins.
DBL
CNFGB register field - doubled-bank.
DC
Device address field in COLC packet.
device
An RDRAM on a Channel.
DEVID
Control register with device address that is
matched against DR, DC, and DX fields.
DM
Device match for ROW packet decode.
doubled-bank
RDRAM with shared sense amp.
DQ
DQA and DQB pins.
DQA
Pins for data byte A.
DQB
Pins for data byte B.
DQS
NAPX register field - PDN/NAP exit.
DR,DR4T,DR4F
Device address field and packet framing
fields in ROWA and ROWR packets.
dualoct
16 bytes - the smallest addressable datum.
DX
Device address field in COLX packet.
field
A collection of bits in a packet.
INIT
Control register with initialization fields.
initialization
Configuring a Channel of RDRAMs so
they are ready to respond to transactions.
LSR
CNFGA register field - low-power self-
refresh.
M
Mask opcode field (COLM/COLX packet).
MA
Field in COLM packet for masking byte A.
MB
Field in COLM packet for masking byte B.
MSK
Mask command in M field.
MVER
Control register - manufacturer ID.
NAP
Power state - needs SCK/CMD wakeup.
NAPR
Nap command in ROP field.
NAPRC
Conditional nap command in ROP field.
NAPXA
NAPX register field - NAP exit delay A.
NAPXB
NAPX register field - NAP exit delay B.
NOCOP
No-operation command in COP field.
NOROP
No-operation command in ROP field.
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