參數(shù)資料
型號(hào)： HY5R256HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 256M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 256M
文件頁數(shù)： 58/64頁
文件大?。?/td> 4542K
代理商： HY5R256HC
58
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Timing Parameters
Table 21: Timing Parameter Summary
Parameter
Description
Min
-40
-800
Min
-45
-800
Min
-45
-711
Min
-53
-600
Max
Units
Figure(s)
t
RC
Row Cycle time of RDRAM banks -the interval between ROWA packets
with ACT commands to the same bank.
28
28
28
28
-
t
CYCLE
Figure 15:
Figure 16:
t
RAS
RAS-asserted time of RDRAM bank - the interval between ROWA packet
with ACT command and next ROWR packet with PRER
a
command to the
same bank.
20
20
20
20
64
μ
s
b
t
CYCLE
Figure 15:
Figure 16:
t
RP
Row Precharge time of RDRAM banks - the interval between ROWR packet
with PRER
a
command and next ROWA packet with ACT command to the
same bank.
8
8
8
8
-
t
CYCLE
Figure 15:
Figure 16:
t
PP
Precharge-to-precharge time of RDRAM device - the interval between suc-
cessive ROWR packets with PRER
a
commands to any banks of the same
device.
8
8
8
8
-
t
CYCLE
Figure 12:
t
RR
RAS-to-RAS time of RDRAM device - the interval between successive
ROWA packets with ACT commands to any banks of the same device.
8
8
8
8
-
t
CYCLE
Figure 13:
t
RCD
RAS-to-CAS Delay - the interval from ROWA packet with ACT command
to COLC packet with RD or WR command). Note - the RAS-to-CAS delay
seen by the RDRAM core (t
RCD-C
) is equal to t
RCD-C
= 1 + t
RCD
because of
differences in the row and column paths through the RDRAM interface.
7
9
7
7
-
t
CYCLE
Figure 15:
Figure 16:
t
CAC
CAS Access delay - the interval from RD command to Q read data. The
equation for t
CAC
is given in the TPARM register in Figure 39:.
8
8
8
8
12
t
CYCLE
Figure 4:
Figure 39:
t
CWD
CAS Write Delay (interval from WR command to D write data.
6
6
6
6
6
t
CYCLE
Figure 4:
t
CC
CAS-to-CAS time of RDRAM bank - the interval between successive COLC
commands).
4
4
4
4
-
t
CYCLE
Figure 15:
Figure 16:
t
PACKET
Length of ROWA, ROWR, COLC, COLM or COLX packet.
4
4
4
4
4
t
CYCLE
Figure 3:
t
RTR
Interval from COLC packet with WR command to COLC packet which
causes retire, and to COLM packet with bytemask.
8
8
8
8
-
t
CYCLE
Figure 17:
t
OFFP
The interval (offset) from COLC packet with RDA command, or from
COLC packet with retire command (after WRA automatic precharge), or
from COLX packet with PREX command to the equivalent ROWR packet
with PRER.The equation for t
OFFP
is given in the TPARM register in Figure
39:.
4
4
4
4
4
t
CYCLE
Figure 14:
Figure 39:
t
RDP
Interval from last COLC packet with RD command to ROWR packet with
PRER.
4
4
4
4
-
t
CYCLE
Figure 15:
t
RTP
Interval from last COLC packet with automatic retire command to ROWR
packet with PRER.
4
4
4
4
-
t
CYCLE
Figure 16:
a. Or equivalent PREC or PREX command. See Figure 14:.
b. This is a constraint imposed by the core, and is therefore in units of
μ
s rather than t
CYCLE
.
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