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參數(shù)資料
| 型號： | HY5R256HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 256M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 256M |
| 文件頁數(shù)： | 36/64頁 |
| 文件大小： | 4542K |
| 代理商： | HY5R256HC |
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36
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
.
Figure 39: TPARM Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
TCAS1..0 - Specifies the t
CAS-C
core parameter in
t
CYCLE
units. This should be “10” (2t
CYCLE
).
TCLS1..0 - Specifies the t
CLS-C
core parameter in
t
CYCLE
units. Should be “10” (2t
CYCLE
).
TCDLY0 - Specifies the t
CDLY0-C
core parameter in
t
CYCLE
units. This adds a programmable delay to Q
(read data) packets, permitting round trip read delay to
all devices to be equalized. This field may be written
with the values “010” (2t
CYCLE
) through “101”
(5t
CYCLE
).
Control Register: TPARM
Address: 048
16
0
0
0
0
0
0
0
0
0
0
0
TCAS
TCLS
The equations relating the core parameters to the
datasheet parameters follow:
t
CAS-C
= 2t
CYCLE
t
CLS-C
= 2t
CYCLE
t
CPS-C
= 1t
CYCLE
Not programmable
t
OFFP
= t
CPS-C
+ t
CAS-C
+ t
CLS-C
- 1t
CYCLE
= 4t
CYCLE
t
RCD
= t
RCD-C
+ 1t
CYCLE
- t
CLS-C
= t
RCD-C
- 1t
CYCLE
t
CAC
= 3t
CYCLE
+ t
CLS-C
+ t
CDLY0-C
+ t
CDLY1-C
(see table below for programming ranges)
TCDLY0
011
011
101
100
TCDLY0
010
010
3t
CYCLE
3t
CYCLE
5t
CYCLE
4t
CYCLE
t
CDLY0-C
3t
CYCLE
2t
CYCLE
010
001
010
010
TCDLY1
000
000
2t
CYCLE
1t
CYCLE
2t
CYCLE
2t
CYCLE
t
CDLY1-C
0t
CYCLE
0t
CYCLE
10t
CYCLE
9t
CYCLE
12t
CYCLE
11t
CYCLE
t
CAC
@ t
CYCLE
= 3.3ns
8t
CYCLE
7t
CYCLE
10t
CYCLE
9t
CYCLE
12t
CYCLE
11t
CYCLE
t
CAC
@ t
CYCLE
= 2.5ns
8t
CYCLE
not allowed
Figure 40: TFRM Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
TFRM3..0 - Specifies the position of the framing point
in t
CYCLE
units. This value must be greater than or
equal to the t
FRM,MIN
parameter. This is the minimum
offset between a ROW packet (which places a device
at ATTN) and the first COL packet (directed to that
device) which must be framed. This field may be
written with the values “0111” (7t
CYCLE
) through
“1010” (10t
CYCLE
). TFRM is usually set to the value
which matches the largest t
RCD,MIN
parameter (modulo
4t
CYCLE
) that is present in an RDRAM in the memory
system. Thus, if an RDRAM with t
RCD,MIN
=
11t
CYCLE
were present, then TFRM would be
programmed to 7t
CYCLE
.
Control Register: TFRM
Address: 049
16
0
0
0
0
0
0
0
0
0
0
0
0
TFRM3..0
Figure 41: TRDLY Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Read/write register.
Reset value is undefined.
TCDLY1 - Specifies the value of the t
CDLY1-C
core
parameter in t
CYCLE
units. This adds a programmable
delay to Q (read data) packets, permitting round trip
read delay to all devices to be equalized. This field may
be written with the values “000” (0t
CYCLE
) through
“010” (2t
CYCLE
). Refer to Figure 39: for more details.
Control Register: TCDLY1
Address: 04a
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCDLY1
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