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參數(shù)資料
| 型號： | HY5R256HC |
| 英文描述： | -|2.5V|8K|40|Direct RDRAM - 256M |
| 中文描述： | - |為2.5V | 8K的| 40 |直接RDRAM的- 256M |
| 文件頁數(shù)： | 42/64頁 |
| 文件大?。?/td> | 4542K |
| 代理商： | HY5R256HC |
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42
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Refresh
RDRAMs, like any other DRAM technology, use volatile
storage cells which must be periodically refreshed. This is
accomplished with the REFA command. Figure 50: shows
an example of this.
The REFA command in the transaction is typically a broad-
cast command (DR4T and DR4F are both set in the ROWR
packet), so that in all devices bank number Ba is activated
with row number REFR, where REFR is a control register in
the RDRAM. When the command is broadcast and ATTN is
set, the power state of the RDRAMs (ATTN or STBY) will
remain unchanged. The controller increments the bank
address Ba for the next REFA command. When Ba is equal
to its maximum value, the RDRAM automatically incre-
ments REFR for the next REFA command.
On average, these REFA commands are sent once every
t
REF
/2
BBIT+RBIT
(where BBIT are the number of bank
address bits and RBIT are the number of row address bits) so
that each row of each bank is refreshed once every t
REF
interval.
The REFA command is equivalent to an ACT command, in
terms of the way that it interacts with other packets (see
Table 9). In the example, an ACT command is sent after t
RR
to address b0, a different (non-adjacent) bank than the REFA
command.
A second ACT command can be sent after a time t
RC
to
address c0, the same bank (or an adjacent bank) as the REFA
command.
Note that a broadcast REFP command is issued a time t
RAS
after the initial REFA command in order to precharge the
refreshed bank in all RDRAMs. After a bank is given a
REFA command, no other core operations (activate or
precharge) should be issued to it until it receives a REFP.
It is also possible to interleave refresh transactions (not
shown). In the figure, the ACT b0 command would be
replaced by a REFA b0 command. The b0 address would be
broadcast to all devices, and would be {Broad-
cast,Ba+2,REFR}. Note that the bank address should skip by
two to avoid adjacent bank interference. A possible bank
incrementing pattern would be: {12, 10, 5, 3, 0, 14, 9, 7, 4, 2,
13, 11, 8, 6, 1, 15, 28, 26, 21, 19, 16, 30, 25, 23, 20, 18, 29,
27, 24, 22, 17, 31}. Every time bank 31 is reached, the
REFA command would automatically increment the REFR
register.
A second refresh mechanism is available for use in PDN and
NAP power states. This mechanism is called self-refresh
mode. When the PDN power state is entered, or when NAP
power state is entered with the NSR control register bit set,
then self-refresh is automatically started for the RDRAM.
Self-refresh uses an internal time base reference in the
RDRAM. This causes an activate and precharge to be
carried out once in every t
REF
/2
BBIT+RBIT
interval. The
REFB and REFR control registers are used to keep track of
the bank and row being refreshed.
Before a controller places an RDRAM into self-refresh
mode, it should perform REFA/REFP refreshes until the
bank address is equal to the last value.(this will be 31 for all
sequences) This ensures that no rows are skipped. Likewise,
when a controller returns an RDRAM to REFA/REFP
refresh, it should start with the minimum bank address value
(12 for the example sequence)
Note that for this RDRAM, the upper bank address bit is not
used. This bit should be set to “0” in all bank address fields,
but with one exception. When REFA and REFP commands
are specified in ROWR packets, it will be necessary to set
the upper bank bit to values other than :0” when other
RDRAMs with no more banks are present on the Channel.
Figure51 illustrates the requirement imposed by the t
BURST
.
parameter. After PDN or NAP (when self-refresh is enabled)
power states are exited, the controller must refresh all banks
of the RDRAM once during the interval t
BURST
after the
restricted interval on the ROW and COL buses. This will
ensure that regardless of the state of self-refresh during PDN
or NAP, the t
REF,MAX
parameter is met for all banks. During
the t
BURST
interval, the banks may be refreshed in a single
burst, or they may be scattered throughout the interval. Note
that the first and last banks to be refreshed in the t
BURST
interval are numbers 12 and 31, in order to match the
example refresh sequence.
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| HY5S2B6DLF-BE | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 2M x 16bits Synchronous DRAM |
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