參數(shù)資料
型號(hào): HYB 39S256400AT
廠商: SIEMENS AG
英文描述: 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動(dòng)態(tài)RAM)
中文描述: 256兆位(4banks × 16兆× 4)同步DRAM(256M(4列× 1,600位× 4)同步動(dòng)態(tài)RAM)的
文件頁(yè)數(shù): 19/42頁(yè)
文件大小: 282K
代理商: HYB 39S256400AT
HYB 39S256400/800/160AT
256-MBit Synchronous DRAM
Data Book
19
1.00
Notes
1. For proper power-up see the operation section of this data sheet.
2. AC timing tests
for LV-TTL versions
have
V
IL
= 0.4 V and
V
IH
= 2.4 V with the timing referenced to
the 1.4 V crossover point. The transition time is measured between
V
IH
and
V
IL
. All AC
measurements assume
t
T
= 1 ns with the AC output load circuit shown in figure below. Specified
t
AC
and
t
OH
parameters are measured with a 50 pF only, without any resistive termination and
with a input signal of 1V / ns edge rate between 0.8 V and 2.0 V.
3. If clock rising time is longer than 1 ns, a time (
t
T
/2
0.5) ns has to be added to this parameter.
4. If
t
T
is longer than 1 ns, a time (
t
T
1) ns has to be added to this parameter.
5. These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)
6. Access time from clock
t
AC
is 4.6 ns for PC133 components with no termination and 0 pF load,
Data out hold time
t
OH
is 1.8 ns for PC133 components with no termination and 0 pF load.
7. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to
t
RC
is satisfied
once the Self Refresh Exit command is registered.
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
t
T
OUTPUT
1.4 V
t
LZ
AC
t
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC
and
t
OH
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB39S256400AT-7.5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM
HYB39S256400AT-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM
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