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參數(shù)資料
| 型號(hào)： | HYB 39S256400AT |
| 廠商： | SIEMENS AG |
| 英文描述： | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動(dòng)態(tài)RAM) |
| 中文描述： | 256兆位（4banks × 16兆× 4）同步DRAM（256M（4列× 1,600位× 4）同步動(dòng)態(tài)RAM）的 |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 282K |
| 代理商： | HYB 39S256400AT |
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HYB 39S256400/800/160AT
256-MBit Synchronous DRAM
Data Book
7
1.00
Signal Pin Description
Pin
Type
Signal Polarity Function
CLK
Input
Pulse
Positive
Edge
The system clock input. All of the SDRAM inputs are
sampled on the rising edge of the clock.
CKE
Input
Level
Active
High
Activates the CLK signal when high and deactivates the
CLK signal when low, thereby initiates either the Power
Down mode, Suspend mode, or the Self Refresh mode.
CS
Input
Pulse
Active
Low
CS enables the command decoder when low and disables
the command decoder when high. When the command
decoder is disabled, new commands are ignored but
previous operations continue.
RAS
CAS
WE
Input
Pulse
Active
Low
When sampled at the positive rising edge of the clock,
CAS, RAS, and WE define the command to be executed by
the SDRAM.
A0 - A12
Input
Level
–
During a Bank Activate command cycle, A0-A12 define the
row address (RA0-RA12) when sampled at the rising clock
edge.
During a Read or Write command cycle, A0-An define the
column address (CA0-CAn) when sampled at the rising
clock edge.CAn depends from the SDRAM organization:
64M x 4 SDRAM CAn = CA9, CA11
(Page Length = 2048 bits)
(Page Length = 1024 bits)
(Page Length = 512 bits)
32M x 8 SDRAM CAn = CA9
16M x 16 SDRAMCAn = CA8
In addition to the column address, A10(= AP) is used to
invoke autoprecharge operation at the end of the burst read
or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in
conjunction with BA0 and BA1 to control which bank(s) to
precharge. If A10 is high, all four banks will be precharged
regardless of the state of BA0 and BA1. If A10 is low, then
BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input
Level
–
Bank Select Inputs. Bank address inputs selects which of
the four banks a command applies to.
DQx
Input
Output
Level
–
Data Input/Output pins operate in the same manner as on
conventional DRAMs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB 39S256800AT | 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動(dòng)態(tài)RAM) |
| HYB 39S256160AT | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動(dòng)態(tài)RAM) |
| HYB 39S256400CT | 256-Mbit(4banks × 16MBit × 4) Synchronous DRAM(256M(4列 × 16M位 × 4)同步動(dòng)態(tài)RAM) |
| HYB 39S256800CT | 256-Mbit(4banks × 8MBit × 8) Synchronous DRAM(256M(4列 × 8M位 × 8)同步動(dòng)態(tài)RAM) |
| HYB 39S256160CT | 256-Mbit(4banks × 4MBit × 16) Synchronous DRAM(256M(4列 × 4M位 × 16)同步動(dòng)態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB39S256400AT-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400AT-8 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400AT-8A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400AT-8B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x4 SDRAM |
| HYB39S256400CT-7.5 | 制造商:Infineon Technologies AG 功能描述:64M X 4 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
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