參數(shù)資料
型號: LAMXO640E-3TN144E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 75/77頁
文件大?。?/td> 0K
描述: IC FPGA 640LUTS 144TQFP
標準包裝: 60
系列: LA-MachXO
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 4.9ns
電壓電源 - 內(nèi)部: 1.14 V ~ 1.26 V
宏單元數(shù): 320
輸入/輸出數(shù): 113
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-TQFP(20x20)
包裝: 托盤
November 2007
Data Sheet DS1003
2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specications and information herein are subject to change without notice.
www.latticesemi.com
7-1
Revision History
Date
Version
Section
Change Summary
April 2006
01.0
Initial release.
May 2006
01.1
Pinout Information
Removed [LOC][0]_PLL_RST from Signal Descriptions table.
PCLK footnote added to appropriate pins in Logic Signal Connections
tables.
November 2006
01.2
DC and Switching
Characteristics
Corrections to MachXO “C” Sleep Mode Timing table - value for
tWSLEEPN (400ns) changed from max. to min. Value for tWAWAKE
(100ns) changed from min. to max.
Added Flash Download Time table.
December 2006
01.3
Architecture
EBR Asynchronous Reset section added.
Pinout Information
Power Supply and NC table: Pin/Ball orientation footnotes added.
February 2007
01.4
Architecture
Updated EBR Asynchronous Reset section.
November 2007
01.5
DC and Switching
Characteristics
Updated sysIO Single-Ended DC Electrical Characteristics table.
Added JTAG Port Timing Waveforms diagram.
Pinout Information
Added Thermal Management text section.
Supplemental
Information
Updated title list.
LA-MachXO Automotive Family Data Sheet
Revision History
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