參數(shù)資料
型號(hào): LAMXO640E-3TN144E
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 38/77頁
文件大?。?/td> 0K
描述: IC FPGA 640LUTS 144TQFP
標(biāo)準(zhǔn)包裝: 60
系列: LA-MachXO
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 4.9ns
電壓電源 - 內(nèi)部: 1.14 V ~ 1.26 V
宏單元數(shù): 320
輸入/輸出數(shù): 113
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應(yīng)商設(shè)備封裝: 144-TQFP(20x20)
包裝: 托盤
3-17
DC and Switching Characteristics
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
Flash Download Time
JTAG Port Timing Specications
Over Recommended Operating Conditions
Figure 3-5. JTAG Port Timing Waveforms
Symbol
Parameter
Min.
Typ.
Max.
Units
tREFRESH
Minimum VCC or VCCAUX
(later of the two supplies)
to Device I/O Active
LCMXO256
0.4
ms
LCMXO640
0.6
ms
LCMXO1200
0.8
ms
LCMXO2280
1.0
ms
Symbol
Parameter
Min.
Max.
Units
fMAX
TCK [BSCAN] clock frequency
25
MHz
tBTCP
TCK [BSCAN] clock pulse width
40
ns
tBTCPH
TCK [BSCAN] clock pulse width high
20
ns
tBTCPL
TCK [BSCAN] clock pulse width low
20
ns
tBTS
TCK [BSCAN] setup time
8
ns
tBTH
TCK [BSCAN] hold time
10
ns
tBTRF
TCK [BSCAN] rise/fall time
50
mV/ns
tBTCO
TAP controller falling edge of clock to output valid
10
ns
tBTCODIS
TAP controller falling edge of clock to output disabled
10
ns
tBTCOEN
TAP controller falling edge of clock to output enabled
10
ns
tBTCRS
BSCAN test capture register setup time
8
ns
tBTCRH
BSCAN test capture register hold time
25
ns
tBUTCO
BSCAN test update register, falling edge of clock to output valid
25
ns
tBTUODIS
BSCAN test update register, falling edge of clock to output disabled
25
ns
tBTUPOEN
BSCAN test update register, falling edge of clock to output enabled
25
ns
Rev. A 0.19
TMS
TDI
TCK
TDO
Data to be
captured
from I/O
Data to be
driven out
to I/O
a
t
a
D
d
il
a
V
a
t
a
D
d
il
a
V
a
t
a
D
d
il
a
V
a
t
a
D
d
il
a
V
Data Captured
tBTCPH
tBTCPL
tBTCOEN
tBTCRS
tBTUPOEN
tBUTCO
tBTUODIS
tBTCRH
tBTCO
tBTCODIS
tBTS
tBTH
tBTCP
相關(guān)PDF資料
PDF描述
LAMXO640C-3TN144E IC FPGA AUTO 640LUTS 144TQFP
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HCC49DREI-S93 CONN EDGECARD 98POS .100 EYELET
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