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參數資料
| 型號： | LAMXO640E-3TN144E |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數： | 11/77頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 640LUTS 144TQFP |
| 標準包裝： | 60 |
| 系列： | LA-MachXO |
| 可編程類型： | 系統內可編程 |
| 最大延遲時間 tpd(1)： | 4.9ns |
| 電壓電源 - 內部： | 1.14 V ~ 1.26 V |
| 宏單元數： | 320 |
| 輸入/輸出數： | 113 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應商設備封裝： | 144-TQFP（20x20） |
| 包裝： | 托盤 |
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2-16
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
of the devices also support differential input buffers. PCI clamps are available on the top Bank I/O buffers. The
PCI clamp is enabled after VCC, VCCAUX, and VCCIO are at valid operating levels and the device has been con-
gured.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
2.
Left and Right sysIO Buffer Pairs
The sysIO buffer pairs in the left and right Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (supporting ratioed and absolute input levels). The devices also have a
differential driver per output pair. The referenced input buffer can also be congured as a differential input
buffer. In these Banks the two pads in the pair are described as “true” and “comp”, where the true pad is asso-
ciated with the positive side of the differential I/O, and the comp (complementary) pad is associated with the
negative side of the differential I/O.
Typical I/O Behavior During Power-up
The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels.
After the POR signal is deactivated, the FPGA core logic becomes active. It is the user’s responsibility to ensure
that all VCCIO Banks are active with valid input logic levels to properly control the output logic states of all the I/O
Banks that are critical to the application. The default conguration of the I/O pins in a blank device is tri-state with a
weak pull-up to VCCIO. The I/O pins will maintain the blank conguration until VCC, VCCAUX and VCCIO have
reached satisfactory levels at which time the I/Os will take on the user-congured settings.
The VCC and VCCAUX supply the power to the FPGA core fabric, whereas the VCCIO supplies power to the I/O buff-
ers. In order to simplify system design while providing consistent and predictable I/O behavior, the I/O buffers
should be powered up along with the FPGA core fabric. Therefore, VCCIO supplies should be powered up before or
together with the VCC and VCCAUX supplies
Supported Standards
The LA-MachXO sysIO buffer supports both single-ended and differential standards. Single-ended standards can
be further subdivided into LVCMOS and LVTTL. The buffer supports the LVTTL, LVCMOS 1.2, 1.5, 1.8, 2.5, and
3.3V standards. In the LVCMOS and LVTTL modes, the buffer has individually congurable options for drive
strength, bus maintenance (weak pull-up, weak pull-down, bus-keeper latch or none) and open drain. BLVDS and
LVPECL output emulation is supported on all devices. The LA-MachXO1200 and LA-MachXO2280 support on-chip
LVDS output buffers on approximately 50% of the I/Os on the left and right Banks. Differential receivers for LVDS,
BLVDS and LVPECL are supported on all Banks of LA-MachXO1200 and LA-MachXO2280 devices. PCI support is
provided in the top Banks of the LA-MachXO1200 and LA-MachXO2280 devices. Table 2-8 summarizes the I/O
characteristics of the devices in the LA-MachXO family.
Tables 2-9 and 2-10 show the I/O standards (together with their supply and reference voltages) supported by the
LA-MachXO devices. For further information on utilizing the sysIO buffer to support a variety of standards please
see the details of additional technical documentation at the end of this data sheet.
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