參數(shù)資料
型號(hào)： LAMXO640E-3TN144E
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 10/77頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 640LUTS 144TQFP
標(biāo)準(zhǔn)包裝： 60
系列： LA-MachXO
可編程類(lèi)型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 4.9ns
電壓電源 - 內(nèi)部： 1.14 V ~ 1.26 V
宏單元數(shù)： 320
輸入/輸出數(shù)： 113
工作溫度： -40°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 144-LQFP
供應(yīng)商設(shè)備封裝： 144-TQFP（20x20）
包裝： 托盤(pán)
2-15
Architecture
Lattice Semiconductor
LA-MachXO Automotive Family Data Sheet
output data signals are multiplexed and provide a single signal to the I/O pin via the sysIO buffer. Figure 2-17
shows the LA-MachXO PIO logic.
The tristate control signal is multiplexed from the output data signals and their complements. In addition a global
signal (TSALL) from a dedicated pad can be used to tristate the sysIO buffer.
The PIO receives an input signal from the pin via the sysIO buffer and provides this signal to the core of the device.
In addition there are programmable elements that can be utilized by the design tools to avoid positive hold times.
Figure 2-17. LA-MachXO PIO Block Diagram
sysIO Buffer
Each I/O is associated with a exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as Banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, TTL, BLVDS, LVDS and LVPECL.
In the LA-MachXO devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are
powered using VCCIO. In addition to the Bank VCCIO supplies, the LA-MachXO devices have a VCC core logic power
supply, and a VCCAUX supply that powers up a variety of internal circuits including all the differential and referenced
input buffers.
LA-MachXO256 and LA-MachXO640 devices contain single-ended input buffers and single-ended output buffers
with complementary outputs on all the I/O Banks.
LA-MachXO1200 and LA-MachXO2280 devices contain two types of sysIO buffer pairs.
1.
Top and Bottom sysIO Buffer Pairs
The sysIO buffer pairs in the top and bottom Banks of the device consist of two single-ended output drivers and
two sets of single-ended input buffers (for ratioed or absolute input levels). The I/O pairs on the top and bottom
PAD
sysIO
Buffer
TO
Programmable
Delay Elements
From Complementary
Pad
1
2
3
4
+
-
Input
Data Signal
From Routing
Fast Output
Note: Buffer 1 tracks with VCCAUX
Buffer 3 tracks with internal 1.2V VREF.
Buffer 4 is available in MachXO1200 and MachXO2280 devices only.
Buffer 2 tracks with VCCIO.
Data signal
TSALL
DO
TS
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