參數(shù)資料
型號(hào)： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 107/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
Chapter 9
Pin Diagram, Listings, and Descriptions
ICS1892, Rev. D, 2/26/01
February 26, 2001
107
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
DPXSEL
24
Input or
Output
Half-Duplex / Full-Duplex Select.
The ‘Pin Type’ for this pin depends on the setting for the HW/SW pin
(pin 23). When the HW/SW pin is set for:
Hardware mode, this pin acts as an input. In this case, when the
signal on this pin is logic:
– Low, this pin selects half-duplex operations.
– High, this pin selects full-duplex operations.
Software mode, this pin acts as an output that indicates the current
status of this pin. In this case, when the signal on this pin is logic:
– Low, this pin indicates that it is set for half-duplex operations.
– High, this pin indicates that it is set for full-duplex operations.
HW/SW
23
Input
Hardware/Software (Select).
When the signal on this pin is logic:
Low, this pin selects Hardware mode operations.
High, this pin selects Software mode operations.
(Stream Cipher) Lock (Acquired).
When the signal on this pin is logic:
Low, the ICS1892 does not have a lock on the data stream.
High, the 1892 has a lock on the data stream.
Link Status.
This pin is used to report the status of the link segment. When the
signal on this pin is logic:
Low, there is no link established.
High, there is a link established.
This pin is mapped according to the interface for which the ICS1892 is
mapped. For the:
Media Independent Interface (MII), the LSTA is mapped as LSTA.
100M Symbol Interface, the LSTA is mapped as SD.
10M Serial Interface, the LSTA is mapped as LSTA.
Link Pulse Interface, the LSTA is mapped as SD.
Media Independent Interface / Stream Interface (Select).
This pin is used in combination with the 10/LP and 10/100SEL pins to
configure the ICS1892 MAC/Repeater Interface. When the signal on
this pin is logic:
Low, this pin configures the MAC/Repeater Interface as a Media
Independent Interface.
High, this pin configures the MAC/Repeater Interface as a Stream
Interface.
LOCK
27
Output
LSTA
21
Output
MII/SI
19
Input
NOD/REP
1
Input
Node/Repeater (Select).
This selection on this pin affects both the SQE test and the Carrier
Sense (CSR) signal. When the signal on this pin is logic:
Low, this pin enables the ICS1892 to default to node operations.
High, this pin enables the ICS1892 to default to repeater
operations.
Table 9-5.
Configuration Pins (
Continued
)
Pin
Name
Pin
Number
Pin
Type
Pin Description
相關(guān)PDF資料
PDF描述
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
ICS1893AF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFI 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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