參數(shù)資料
型號： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 18/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
ICS1892, Rev. D, 2/26/01
February 26, 2001
18
Chapter 5
Operating Modes Overview
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
5.1
Reset Operations
This section first discusses reset operations in general and then specific ways in which the ICS1892 can be
configured for various reset options.
5.1.1
General Reset Operations
The following reset operations apply to all the specific ways in which the ICS1892 can be reset, which are
discussed in
Section 5.1.2, “Specific Reset Operations”
.
5.1.1.1
Entering Reset
When the ICS1892 enters a reset condition (either through hardware, power-on reset, or software), it does
the following:
1.
2.
3.
4.
5.
6.
Isolates the MAC/Repeater Interface input pins
Drives all MAC/Repeater Interface output pins low
Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
Initializes all its internal modules and state machines to their default states
Enters the power-down state
Initializes all internal latching low (LL), latching high (LH), and latching maximum (LMX) Management
Register bits to their default values
5.1.1.2
Exiting Reset
When the ICS1892 exits a reset condition, it does the following:
1.
2.
Exits the power-down state
Latches the Serial Management Port Address of the ICS1892 into the Extended Control Register, bits
16.10:6.
[See
Section 8.11.3, “PHY Address (bits 16.10:6)”
.]
Enables all its internal modules and state machines
Sets all Management Register bits to either (1) their default values or (2) the values specified by their
associated ICS1892 input pins, as determined by the HW/SW pin
Enables the Twisted-Pair Transmit pins (TP_TXP and TP_TXN)
Resynchronizes both its Transmit and Receive Phase-Locked Loops, which provide its transmit clock
(TXCLK) and receive clock (RXCLK)
Releases all MAC/Repeater Interface pins, which takes a maximum of 640 ns after the reset condition
is removed
3.
4.
5.
6.
7.
5.1.1.3
Hot Insertion
As with the ICS 1890, the ICS1892 reset design supports ‘hot insertion’ of its MII. (That is, the ICS1892 can
connect its MAC/Repeater Interface to a MAC/repeater while power is already applied to the
MAC/repeater.)
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