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參數(shù)資料
| 型號： | ICS1892Y-10 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 38/148頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y-10 |
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ICS1892, Rev. D, 2/26/01
February 26, 2001
38
Chapter 7
Functional Blocks
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7.2.4
Auto-Negotiation: Reset and Restart
If enabled, execution of the ICS1892 auto-negotiation process occurs at power-up and upon management
request. There are two primary ways to begin the Auto-Negotiation state machine:
ICS1892 reset
Auto-Negotiation Restart
7.2.4.1
Auto-Negotiation Reset
During a reset, the ICS1892 initializes its Auto-Negotiation sublayer modules to their default states. (That
is, the Auto-Negotiation Arbitration State Machine and the Auto-Negotiation Progress Monitor reset to their
idle states.) In addition, the Auto-Negotiation Progress Monitor status bits are all set to logic zero. This
action
occurs for any type of reset (hardware reset, software reset, or power-on reset).
7.2.4.2
Auto-Negotiation Restart
As with a reset, during an Auto-Negotiation restart, the ICS1892 initializes the Auto-Negotiation Arbitration
State Machine and the Auto-Negotiation Progress Monitor modules to their default states. However, during
an Auto-Negotiation Restart, the Auto-Negotiation Progress Monitor status bits maintain their current state.
Only three events can alter the state of the Auto-Negotiation Progress Monitor status bits after a Restart:
(1) an STA read operation, (2) a reset, or (3) the Auto-Negotiation Arbitration State Machine progressing to
a higher state or value.
The Auto-Negotiation Progress Monitor Status bits change only if they are progressing to a state with a
value greater than their current state (that is, a state with a higher logical value than that of their current
state). For a detailed explanation of these bits and their operation, see
Section 7.2.5, “Auto-Negotiation:
Progress Monitor”
.
After the Auto-Negotiation Arbitration State Machine reaches its final state (which is Auto-Negotiation
Complete), only an STA read of the QuickPoll Detailed Status Register or an ICS1892 reset can alter these
status bits.
Any one of the following situations initiate a restart of the ICS1892 Auto-Negotiation sublayer:
A link failure
In software mode (that is, HW/SW pin is logic one), either of the following actions initiate a restart of the
ICS1892 Auto-Negotiation sublayer:
– Writing a logic one to the Control Register’s Restart Auto-Negotiation bit (bit 0.9), which is a self-
clearing bit.
– Toggling the Control Register’s Auto-Negotiation Enable bit (bit 0.12) from a logic one to a logic zero,
and back to a logic one.
In hardware mode (that is, HW/SW pin is a logic zero), toggling the ANSEL (Auto-Negotiation Select) pin
from a logic one to a logic zero, and back to a logic one.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
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| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFI | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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