參數(shù)資料
型號(hào)： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 92/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
ICS1892, Rev. D, 2/26/01
February 26, 2001
92
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.12.5
PLL Lock Error (bit 17.9)
The Phase Locked Loop (PLL) Lock Error bit indicates to an STA whether the ICS1892 has ever
experienced a PLL Lock Error. A PLL Lock Error occurs when a the PLL fails to lock onto the incoming
100Base data stream. If this bit is set to a logic:
Zero, it indicates that a PLL Lock Error has not occurred since the last read of this register.
One, it indicates that a PLL Lock Error has occurred after the last read of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
This bit has no definition in 10Base-T mode.
8.12.6
False Carrier (bit 17.8)
The False Carrier bit indicates to an STA the detection of a False Carrier by the ICS1892 in 100Base mode.
A False Carrier occurs when the ICS1892 begins evaluating potential data on the incoming 100Base data
stream, only to learn that it was not a valid /J/K/. If this bit is set to a logic:
Zero, it indicates that a False Carrier has not been detected since the last read of this register.
One, it indicates that a False Carrier was detected since the last read of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
This bit has no definition in 10Base-T mode.
8.12.7
Invalid Symbol (bit 17.7)
The Invalid Symbol bit indicates to an STA the detection of an Invalid Symbol in a 100Base data stream by
the ICS1892.
During reception of a valid packet, the ICS1892 examines each Symbol to ensure that the data being
passed to the MAC/Repeater Interface is error free. If an error occurs, the ICS1892 indicates this condition
to the MAC/repeater. An Invalid Symbol occurs when the ICS1892 evaluates a valid packet and finds an
Invalid Symbol in the data.
If this bit is set to a logic:
Zero, it indicates an Invalid Symbol has not been detected since the last read of this register.
One, it indicates an Invalid Symbol was detected since the last read of this register.
This bit is a latching high bit. (For more information on latching high and latching low bits, see
Section
8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Note:
This bit has no definition in 10Base-T mode.
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