參數(shù)資料
型號： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 89/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
Chapter 8
Management Register Set
ICS1892, Rev. D, 2/26/01
February 26, 2001
89
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.12
Register 17: Quick Poll Detailed Status Register
Table 8-18
lists the bits for the Quick-Poll Detailed Status Register. This register is a 16-bit read-only
register used to provide an STA with detailed status of the ICS1892 operations. During reset, it is initialized
to pre-defined default values.
Note:
1.
2.
For an explanation of acronyms used in
Table 8-18
, see
Chapter 1, “Abbreviations and Acronyms”
.
Most of this register’s bits are latching high or latching low, which allows the ICS1892 to capture and
save the occurrence of an event for an STA to read. (For more information on latching high and latching
low bits, see
Section 8.1.4.1, “Latching High Bits”
and
Section 8.1.4.2, “Latching Low Bits”
.)
Although some of these status bits are redundant with other management registers, the ICS1892
provides this group of bits to minimize the number of Serial Management Cycles required to collect the
status data.
During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
3.
4.
Table 8-18.
Quick Poll Detailed Status Register (register 17 [0x11])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF
De-
fault
Hex
17.15
Data rate
10 Mbps
100 Mbps
RO
–
–
–
17.14
Duplex
Half duplex
Full duplex
RO
–
–
17.13
Auto-Negotiation
Progress Monitor Bit 2
Reference Decode Table
Reference Decode Table
RO
LMX
0
17.12
Auto-Negotiation
Progress Monitor Bit 1
Reference Decode Table
Reference Decode Table
RO
LMX
0
17.11
Auto-Negotiation
Progress Monitor Bit 0
Reference Decode Table
Reference Decode Table
RO
LMX
0
0
17.10
100Base-TX signal
lost
Valid signal
Signal lost
RO
LH
0
17.9
Phase-Locked Loop
locked
PLL locked
PLL failed to lock
RO
LH
0
17.8
False Carrier detect
Normal Carrier or Idle
False Carrier
RO
LH
0
17.7
Invalid symbol
detected
Valid symbols observed
Invalid symbol received
RO
LH
0
0
17.6
Halt Symbol detected
No Halt Symbol received
Halt Symbol received
RO
LH
0
17.5
Premature End
detected
Normal data stream
Stream contained two
IDLE symbols
RO
LH
0
17.4
Auto-Negotiation
complete
Auto-Negotiation in
process
Auto-Negotiation
complete
RO
–
0
17.3
100Base-TX signal
detect
No signal present
Signal present
RO
–
0
0
17.2
Jabber detect
No jabber detected
Jabber detected
RO
LH
0
17.1
Remote fault
No remote fault detected
Remote fault detected
RO
LH
0
17.0
Link Status
Link is not valid
Link is valid
RO
LL
0
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ICS1893AFI 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:PHYceiver™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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