參數(shù)資料
型號： ICS1892Y-10
英文描述： 10Base-T/100Base-TX Integrated PHYceiver
文件頁數(shù)： 88/148頁
文件大?。?/td> 816K
代理商： ICS1892Y-10
ICS1892, Rev. D, 2/26/01
February 26, 2001
88
Chapter 8
Management Register Set
ICS1892 Data Sheet
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
8.11.7
Invalid Error Code Test (bit 16.2)
The Invalid Error Code Test bit allows an STA to force the ICS1892 to transmit symbols that are typically
classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the
serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC
4B/5B definition.
When this bit is logic:
Zero, the ISO/IEC defined 4B/5B translation takes place.
One – and the TXER signal is asserted by the MAC/repeater – the MII input nibbles are translated
according to
Table 8-17
.
8.11.8
ICS Reserved (bit 16.1)
See
Section 8.11.2, “ICS Reserved (bits 16.14:11)”
, the text for which also applies here.
8.11.9
Stream Cipher Disable (bit 16.0)
The Stream Cipher Disable bit allows an STA to control whether the ICS1892 employs the Stream Cipher
Scrambler in the transmit and receive data paths. When this bit is set to logic:
Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.
One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data
stream (for example, the ICS1892 transmits unscrambled IDLES, and so forth.
Note:
The Stream Cipher Scrambler can be used only for 100-MHz operations.
Table 8-17.
Invalid Error Code Translation Table
Symbol
Meaning
MII Input
Nibble
Translation
V
Invalid Code
0000
00000
V
Invalid Code
0001
00001
V
Invalid Code
0010
00010
V
Invalid Code
0011
00011
H
Error
0100
00100
V
Invalid Code
0101
00101
V
Invalid Code
0110
00110
R
ESD
0111
00111
V
Invalid Code
1000
00000
T
ESD
1001
01101
V
Invalid Code
1010
01100
K
SSD
1011
10001
V
Invalid Code
1100
10000
V (S)
Invalid Code
1101
11001
J
SSD
1110
11000
I
Idle
1111
11111
相關(guān)PDF資料
PDF描述
ICS1892Y-14 10Base-T/100Base-TX Integrated PHYceiver
ICS1893AF 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893Y-10 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM
ICS1893 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS1892Y-14 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver
ICS1893 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver
ICS1893_09 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver?
ICS1893AF 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
ICS1893AFI 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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