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參數(shù)資料
| 型號： | ICS1892Y-10 |
| 英文描述： | 10Base-T/100Base-TX Integrated PHYceiver |
| 文件頁數(shù)： | 57/148頁 |
| 文件大?。?/td> | 816K |
| 代理商： | ICS1892Y-10 |
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Chapter 7
Functional Blocks
ICS1892, Rev. D, 2/26/01
February 26, 2001
57
ICS1892
2000-2001, Integrated Circuit Systems, Inc.
All rights reserved.
7.6.2.6
Management Frame Turnaround
A valid Management Frame includes a turnaround field (TA), which is a 2-bit time space between the
REGAD field and the Data field. This field requires two bit times and allows the ICS1892 and the STA to
avoid contentions during read transactions. During an operation that is a:
Read, the ICS1892 remains in the high-impedance state during the first bit time and subsequently drives
the MDIO pin to logic zero for the second bit time.
Write, the ICS1892 waits while the STA transmits a logic one, followed by a logic zero on the MDIO
signal.
7.6.2.7
Management Frame Data
A valid Management Frame includes a 16-bit Data field for exchanging data between the Management
Registers, and the STA. All Management Registers are 16 bits wide, matching the width of the Data field.
The first Data bit transmitted and received is the most-significant bit of a Management Register, bit X.15.
During a transaction that is a:
Read, OP is 10b and the ICS1892 obtains the value of the register identified in the REGAD field and
returns the Data to the STA synchronously with the MDC cycles.
Write, OP is 01b and the ICS1892 stores the value of the Data field in the register identified in the
REGAD field.
If the STA attempts to:
Read from a non-existent ICS1892 register, the ICS1892 returns logic zero for all bits in the Data field.
Write to a non-existent ICS1892 register, the ICS1892 isolates the Data field.
7.6.2.8
Idle
MDIO is idle during the time between STA transactions. During this idle time, the ICS1892 disables its
tri-state drivers and the MDIO pin enters a high-impedance state. The ISO/IEC 8802-3 standard requires
that the signal be idle for at least one bit time between management transactions. However, the ICS1892
does not have this limitation as it can support a continual bit stream on its MDIO.
相關PDF資料 |
PDF描述 |
|---|---|
| ICS1892Y-14 | 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893AF | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893Y-10 | 3.3V 10Base-T/100Base-TX Integrated PHYceiverTM |
| ICS1893 | 3.3-V 10Base-T/100Base-TX Integrated PHYceiver⑩ |
| ICS2002 | Wavedec Digital Audio Codec |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ICS1892Y-14 | 制造商:ICS 制造商全稱:ICS 功能描述:10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver |
| ICS1893_09 | 制造商:ICS 制造商全稱:ICS 功能描述:3.3-V 10Base-T/100Base-TX Integrated PHYceiver? |
| ICS1893AF | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
| ICS1893AFI | 功能描述:PHYCEIVER LOW PWR 3.3V 48-SSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:PHYceiver™ 標準包裝:1,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:16-SOIC 包裝:帶卷 (TR) |
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